linux-kernel - Re: [PATCH v2 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document optional aux clock

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Message-ID: <84cc6341-a2c1-4e3c-8c9e-2bc6589c52a6@mailbox.org>
Date: Mon, 12 May 2025 22:42:20 +0200
From: Marek Vasut <marek.vasut@...lbox.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
 Marek Vasut <marek.vasut+renesas@...lbox.org>
Cc: linux-arm-kernel@...ts.infradead.org,
 Niklas Söderlund <niklas.soderlund+renesas@...natech.se>,
 Krzysztof Wilczyński <kw@...ux.com>,
 Rafał Miłecki <rafal@...ecki.pl>,
 Aradhya Bhatia <a-bhatia1@...com>, Bjorn Helgaas <bhelgaas@...gle.com>,
 Conor Dooley <conor+dt@...nel.org>,
 Geert Uytterhoeven <geert+renesas@...der.be>,
 Heiko Stuebner <heiko@...ech.de>, Junhao Xie <bigfoot@...ssfun.cn>,
 Kever Yang <kever.yang@...k-chips.com>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
 Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Magnus Damm <magnus.damm@...il.com>,
 Neil Armstrong <neil.armstrong@...aro.org>, Rob Herring <robh@...nel.org>,
 Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v2 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document
 optional aux clock

On 5/9/25 9:37 PM, Manivannan Sadhasivam wrote:
> On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote:
>> Document 'aux' clock which are used to supply the PCIe bus. This
>> is useful in case of a hardware setup, where the PCIe controller
>> input clock and the PCIe bus clock are supplied from the same
>> clock synthesiser, but from different differential clock outputs:
> 
> How different is this clock from the 'reference clock'? I'm not sure what you
> mean by 'PCIe bus clock' here. AFAIK, endpoint only takes the reference clock
> and the binding already has 'ref' clock for that purpose. So I don't understand
> how this new clock is connected to the endpoint device.

See the ASCII art below , CLK_DIF0 is 'ref' clock that feeds the 
controller side, CLK_DIF1 is the bus (or 'aux') clock which feeds the 
bus (or endpoint) side. Both clock come from the same clock synthesizer, 
but from two separate clock outputs of the synthesizer.

>>   ____________                    _____________
>> | R-Car PCIe |                  | PCIe device |
>> |            |                  |             |
>> |    PCIe RX<|==================|>PCIe TX     |
>> |    PCIe TX<|==================|>PCIe RX     |
>> |            |                  |             |
>> |   PCIe CLK<|======..  ..======|>PCIe CLK    |
>> '------------'      ||  ||      '-------------'
>>                      ||  ||
>>   ____________       ||  ||
>> |  9FGV0441  |      ||  ||
>> |            |      ||  ||
>> |   CLK DIF0<|======''  ||
>> |   CLK DIF1<|==========''
>> |   CLK DIF2<|
>> |   CLK DIF3<|
>> '------------'