linux-kernel - Re: [PATCH v3 18/23] ACPI: RISC-V: Add support to update gsi range

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Message-ID: <aCGjuc9AmZaKBGg5@smile.fi.intel.com>
Date: Mon, 12 May 2025 10:31:05 +0300
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Anup Patel <apatel@...tanamicro.com>
Cc: Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Jassi Brar <jassisinghbrar@...il.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	"Rafael J . Wysocki" <rafael@...nel.org>,
	Mika Westerberg <mika.westerberg@...ux.intel.com>,
	Linus Walleij <linus.walleij@...aro.org>,
	Bartosz Golaszewski <brgl@...ev.pl>,
	Uwe Kleine-König <ukleinek@...nel.org>,
	Palmer Dabbelt <palmer@...belt.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Len Brown <lenb@...nel.org>, Sunil V L <sunilvl@...tanamicro.com>,
	Rahul Pathak <rpathak@...tanamicro.com>,
	Leyfoon Tan <leyfoon.tan@...rfivetech.com>,
	Atish Patra <atish.patra@...ux.dev>,
	Andrew Jones <ajones@...tanamicro.com>,
	Samuel Holland <samuel.holland@...ive.com>,
	Anup Patel <anup@...infault.org>, linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 18/23] ACPI: RISC-V: Add support to update gsi range

On Sun, May 11, 2025 at 07:09:34PM +0530, Anup Patel wrote:
> From: Sunil V L <sunilvl@...tanamicro.com>
> 
> Some RISC-V interrupt controllers like RPMI based system MSI interrupt
> controllers do not have MADT entry defined. These interrupt controllers
> exist only in the namespace. ACPI spec defines _GSB method to get the
> GSI base of the interrupt controller, However, there is no such standard
> method to get the GSI range. To support such interrupt controllers, set
> the GSI range of such interrupt controllers to non-overlapping range and
> provide API for interrupt controller driver to update it with proper
> value.

...

> +static inline int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs)
> +{
> +	return -1;

Why not using the defined error code?

> +}

...

> +int riscv_acpi_update_gsi_range(u32 gsi_base, u32 nr_irqs)
> +{
> +	struct riscv_ext_intc_list *ext_intc_element;
> +
> +	list_for_each_entry(ext_intc_element, &ext_intc_list, list) {
> +		if (gsi_base == ext_intc_element->gsi_base &&
> +		    (ext_intc_element->flag & RISCV_ACPI_INTC_FLAG_PENDING)) {
> +			ext_intc_element->nr_irqs = nr_irqs;
> +			ext_intc_element->flag &= ~RISCV_ACPI_INTC_FLAG_PENDING;
> +			return 0;
> +		}
> +	}

> +	return -1;

Ditto.

> +}

...

> +	/* If nr_irqs is zero, indicate it in flag and set to max range possible */
> +	if (!nr_irqs) {

Make conditional positive.

> +		ext_intc_element->flag |= RISCV_ACPI_INTC_FLAG_PENDING;
> +		ext_intc_element->nr_irqs =  U32_MAX - ext_intc_element->gsi_base;

One space too many.

> +	} else {
> +		ext_intc_element->nr_irqs = nr_irqs;
> +	}

-- 
With Best Regards,
Andy Shevchenko