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Message-Id: <20250513152155.1590689-1-parth105105@gmail.com>
Date: Tue, 13 May 2025 17:21:55 +0200
From: Parth Pancholi <parth105105@...il.com>
To: Nishanth Menon <nm@...com>,
	Vignesh Raghavendra <vigneshr@...com>,
	Tero Kristo <kristo@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Siddharth Vadapalli <s-vadapalli@...com>
Cc: Parth Pancholi <parth.pancholi@...adex.com>,
	linux-arm-kernel@...ts.infradead.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH v3] arm64: dts: ti: k3-j784s4-j742s2-main-common: Add ACSPCIE1 node

From: Parth Pancholi <parth.pancholi@...adex.com>

The ACSPCIE1 module on TI's J784S4 SoC is capable of driving the reference
clock required by the PCIe Endpoint device. It is an alternative to on-
board and external reference clock generators.
Add the device-tree node for the same.

Signed-off-by: Parth Pancholi <parth.pancholi@...adex.com>
---
v3: Split SoC support; board-specific changes to follow with Toradex Aquila AM69 upstream addition.
v2: https://lore.kernel.org/all/20250404101234.2671147-1-parth105105@gmail.com/
v1: https://lore.kernel.org/all/20250320122259.525613-1-parth105105@gmail.com/
---
 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index 363d68fec387..d17f365947ed 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -131,6 +131,11 @@ acspcie0_proxy_ctrl: clock-controller@...90 {
 			compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
 			reg = <0x1a090 0x4>;
 		};
+
+		acspcie1_proxy_ctrl: clock-controller@...94 {
+			compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
+			reg = <0x1a094 0x4>;
+		};
 	};
 
 	main_ehrpwm0: pwm@...0000 {
-- 
2.34.1


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