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Message-ID: <1db93ab7-3974-49a7-8816-a495ed52888f@quicinc.com>
Date: Tue, 13 May 2025 21:01:20 +0530
From: Akhil P Oommen <quic_akhilpo@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Rob Clark
	<robdclark@...il.com>, Sean Paul <sean@...rly.run>,
        Konrad Dybcio
	<konradybcio@...nel.org>,
        Abhinav Kumar <quic_abhinavk@...cinc.com>,
        "Marijn
 Suijten" <marijn.suijten@...ainline.org>,
        David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
        Maarten Lankhorst
	<maarten.lankhorst@...ux.intel.com>,
        Maxime Ripard <mripard@...nel.org>,
        Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Dmitry Baryshkov <lumag@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
        <freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, Jie Zhang <quic_jiezh@...cinc.com>
Subject: Re: [PATCH v4 2/3] arm64: dts: qcom: qcs8300: Add gpu and gmu nodes

On 5/13/2025 2:18 AM, Konrad Dybcio wrote:
> On 5/9/25 9:21 AM, Akhil P Oommen wrote:
>> From: Jie Zhang <quic_jiezh@...cinc.com>
>>
>> Add gpu and gmu nodes for qcs8300 chipset.
>>
>> Signed-off-by: Jie Zhang <quic_jiezh@...cinc.com>
>> Signed-off-by: Akhil P Oommen <quic_akhilpo@...cinc.com>
>> ---
> 
> 
>>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 91 +++++++++++++++++++++++++++++++++++
>>  1 file changed, 91 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> index 40771b062e8d7010dd93d7cc7b3db73cfa16bfdb..1dbccb9a0c75366aa6986b6adb4feb6164ee8845 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> @@ -2660,6 +2660,97 @@ serdes0: phy@...9000 {
>>  			status = "disabled";
>>  		};
>>  
>> +		gpu: gpu@...0000 {
>> +			compatible = "qcom,adreno-623.0", "qcom,adreno";
>> +			reg = <0x0 0x03d00000 0x0 0x40000>,
> 
> I haven't noticed it up until now.. this should be moved up in the file
> to sort the nodes by unit address (the serdes node above is 0x089.., gpu
> is 0x03d..)

Looks like GPUCC block got misplaced too. Will fix.

> 
> Otherwise, please check if there are freq fuses on this platform, if not,
> feel free to add:
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>

Thanks. We have the SKU related data available. We will add those too in
the next revision.

-Akhil
> 
> Konrad
> 


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