lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <aCL8BxpHr5OpT04k@gondor.apana.org.au>
Date: Tue, 13 May 2025 16:00:07 +0800
From: Herbert Xu <herbert@...dor.apana.org.au>
To: T Pratham <t-pratham@...com>
Cc: "David S. Miller" <davem@...emloft.net>,
	Kamlesh Gurudasani <kamlesh@...com>,
	Vignesh Raghavendra <vigneshr@...com>,
	Praneeth Bajjuri <praneeth@...com>,
	Manorit Chawdhry <m-chawdhry@...com>, linux-kernel@...r.kernel.org,
	linux-crypto@...r.kernel.org
Subject: Re: [PATCH v4 2/2] crypto: ti: Add driver for DTHE V2 AES Engine
 (ECB, CBC)

On Thu, May 08, 2025 at 03:37:41PM +0530, T Pratham wrote:
>
> +static int dthe_cipher_init_tfm(struct crypto_skcipher *tfm)
> +{
> +	struct dthe_tfm_ctx *ctx = crypto_skcipher_ctx(tfm);
> +	struct dthe_data *dev_data = dthe_get_dev(ctx);
> +
> +	void __iomem *aes_base_reg = dev_data->regs + DTHE_P_AES_BASE;
> +	u32 aes_irqenable_val = readl_relaxed(aes_base_reg + DTHE_P_AES_IRQENABLE);
> +	u32 aes_sysconfig_val = readl_relaxed(aes_base_reg + DTHE_P_AES_SYSCONFIG);
> +
> +	memzero_explicit(ctx, sizeof(*ctx));
> +	ctx->dev_data = dev_data;
> +	ctx->ctx_info.aes_ctx = kzalloc(sizeof(*ctx->ctx_info.aes_ctx), GFP_KERNEL);
> +	if (!ctx->ctx_info.aes_ctx)
> +		return -ENOMEM;

The ctx_info union should just become part of ctx instead of a
separate allocation.

> +	crypto_skcipher_set_reqsize(tfm, sizeof(struct dthe_aes_req_ctx));

Please set cra_reqsize instead in the algorithm.

> +	aes_sysconfig_val |= DTHE_AES_SYSCONFIG_DMA_DATA_IN_OUT_EN;
> +	writel_relaxed(aes_sysconfig_val, aes_base_reg + DTHE_P_AES_SYSCONFIG);
> +
> +	aes_irqenable_val |= DTHE_AES_IRQENABLE_EN_ALL;
> +	writel_relaxed(aes_irqenable_val, aes_base_reg + DTHE_P_AES_IRQENABLE);

This does not look right.  The tfm allocation happens once for each
key, and they could be done concurrently.  You should not be operating
on the hardware in the init_tfm function.

Cheers,
-- 
Email: Herbert Xu <herbert@...dor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ