linux-kernel - Re: [PATCH v3 0/4] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

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Message-ID: <CACRpkda57USe-6zkYKsOfKZcfZx-0DBa-dP2OxkoGsy+tLfHxA@mail.gmail.com>
Date: Tue, 13 May 2025 14:53:51 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Lijuan Gao <quic_lijuang@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Jingyi Wang <quic_jingyw@...cinc.com>, kernel@...cinc.com, linux-arm-msm@...r.kernel.org, 
	linux-gpio@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, 
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, 
	Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v3 0/4] Correct the number of GPIOs in gpio-ranges for
 QCS615 and QCS8300

On Tue, May 6, 2025 at 8:23 AM Lijuan Gao <quic_lijuang@...cinc.com> wrote:

> The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed
> through the GPIO framework. It is expected to be wired to the reset pin
> of the primary UFS memory so that the UFS driver can toggle it.
>
> The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The
> QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to
> 124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
> gpio-rangs to 134.
>
> Signed-off-by: Lijuan Gao <quic_lijuang@...cinc.com>

Patches applied for v6.16!

Yours,
Linus Walleij