Message-ID: <CAMuHMdWa_GuHmw0wRjMJi8ydcn-YTapruWKfoX96FBZHhveQHg@mail.gmail.com>
Date: Tue, 13 May 2025 16:07:36 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Claudiu Beznea <claudiu.beznea@...on.dev>
Cc: mturquette@...libre.com, sboyd@...nel.org, robh@...nel.org, 
	krzk+dt@...nel.org, conor+dt@...nel.org, magnus.damm@...il.com, 
	linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH 3/7] clk: renesas: rzg2l-cpg: Add support for MSTOP in
 clock enable/disable API

Hi Claudiu,

On Tue, 13 May 2025 at 14:34, Claudiu Beznea <claudiu.beznea@...on.dev> wrote:
> On 09.05.2025 15:34, Geert Uytterhoeven wrote:
> > On Fri, 9 May 2025 at 12:54, Claudiu Beznea <claudiu.beznea@...on.dev> wrote:
> >> On 07.05.2025 18:42, Geert Uytterhoeven wrote:
> >>> On Thu, 10 Apr 2025 at 16:06, Claudiu <claudiu.beznea@...on.dev> wrote:
> >>>> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> >>>>
> >>>> The RZ/{G2L, V2L, G3S} CPG versions support a feature called MSTOP. Each
> >>>> module has one or more MSTOP bits associated with it, and these bits need
> >>>> to be configured along with the module clocks. Setting the MSTOP bits
> >>>> switches the module between normal and standby states.
> >>>>
> >>>> Previously, MSTOP support was abstracted through power domains
> >>>> (struct generic_pm_domain::{power_on, power_off} APIs). With this
> >>>> abstraction, the order of setting the MSTOP and CLKON bits was as follows:
> >>>>
> >>>> Previous Order:
> >>>> A/ Switching to Normal State (e.g., during probe):
> >>>> 1/ Clear module MSTOP bits
> >>>> 2/ Set module CLKON bits
> >>>>
> >>>> B/ Switching to Standby State (e.g., during remove):
> >>>> 1/ Clear CLKON bits
> >>>> 2/ Set MSTOP bits
> >>>>
> >>>> However, in some cases (when the clock is disabled through devres), the
> >>>> order may have been (due to the issue described in link section):
> >>>>
> >>>> 1/ Set MSTOP bits
> >>>> 2/ Clear CLKON bits
> >>>>
> >>>> Recently, the hardware team has suggested that the correct order to set
> >>>> the MSTOP and CLKON bits is:
> >>>>
> >>>> Updated Order:
> >>>> A/ Switching to Normal State (e.g., during probe):
> >>>> 1/ Set CLKON bits
> >>>> 2/ Clear MSTOP bits
> >>>>
> >>>> B/ Switching to Standby State (e.g., during remove):
> >>>> 1/ Set MSTOP bits
> >>>> 2/ Clear CLKON bits
> >>>>
> >>>> To prevent future issues due to incorrect ordering, the MSTOP setup has
> >>>> now been implemented in rzg2l_mod_clock_endisable(), ensuring compliance
> >>>> with the sequence suggested in Figure 41.5: Module Standby Mode Procedure
> >>>> from the RZ/G3S HW manual.
> >>>>
> >>>> Additionally, since multiple clocks of a single module may be mapped to a
> >>>> single MSTOP bit, MSTOP setup is reference-counted.
> >>>>
> >>>> Furthermore, as all modules start in the normal state after reset, if the
> >>>> module clocks are disabled, the module state is switched to standby. This
> >>>> prevents keeping the module in an invalid state, as recommended by the
> >>>> hardware team.
> >>>>
> >>>> Link: https://lore.kernel.org/all/20250215130849.227812-1-claudiu.beznea.uj@bp.renesas.com/
> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> >>>
> >>> Thanks for your patch!
> >>>
> >>>> --- a/drivers/clk/renesas/rzg2l-cpg.c
> >>>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> >
> >>>> +/* Need to be called with a lock held to avoid concurrent access to mstop->refcnt. */
> >>>> +static void rzg2l_mod_clock_module_set_state(struct mstp_clock *clock,
> >>>> +                                            bool standby)
> >>>> +{
> >>>> +       struct rzg2l_cpg_priv *priv = clock->priv;
> >>>> +       struct mstop *mstop = clock->mstop;
> >>>> +       bool update = false;
> >>>> +       u32 value;
> >>>> +
> >>>> +       if (!mstop)
> >>>> +               return;
> >>>> +
> >>>> +       value = MSTOP_MASK(mstop->conf) << 16;
> >>>> +
> >>>> +       if (standby) {
> >>>> +               unsigned int criticals = 0;
> >>>> +
> >>>> +               for (u8 i = 0; i < clock->num_shared_mstop_clks; i++) {
> >>>
> >>> unsigned int
> >>>
> >>>> +                       struct mstp_clock *clk = clock->shared_mstop_clks[i];
> >>>> +
> >>>> +                       if (clk->critical)
> >>>> +                               criticals++;
> >>>> +               }
> >>>> +
> >>>> +               /* Increment if clock is critical, too. */
> >>>> +               if (clock->critical)
> >>>> +                       criticals++;
> >>>
> >>> If clock->shared_mstop_clks[] would include the current clock, then
> >>> (a) this test would not be needed, and
> >>
> >> Agree!
> >>
> >>> (b) all clocks sharing the same mstop could share a single
> >>>     clock->shared_mstop_clks[] array.
> >>
> >> I'll look into this but I'm not sure how should I do it w/o extra
> >> processing at the end of registering all the clocks. FWICT, that would
> >> involve freeing some shared_mstop_clks arrays and using a single reference
> >> as the shared_mstop_clks[] is updated after every clock is registered. Can
> >> you please let me know if this what you are thinking about?
> >
> > Currently, when detecting two clocks share the same mstop,
> > you (re)allocate each clock's shared_mstop_clks[], and add the
> > other clock:
> >
> >     rzg2l_cpg_add_shared_mstop_clock(priv->dev, clock, clk);
> >     rzg2l_cpg_add_shared_mstop_clock(priv->dev, clk, clock);
> >
> > Instead, call rzg2l_cpg_add_shared_mstop_clock() once, and modify
> > rzg2l_cpg_add_shared_mstop_clock() to not only realloc the target's
> > shared_mstop_clks[], but also loop over all its existing entries,
> > and update their shared_mstop_clks[] pointers.
> I tried this approach but w/o complicated further the code I can't keep
> track of whether the "to be updated" (not reallocated) shared_mstop_clks[]
> pointers were previously updated pointers or devm_krealloc()'ed ones. I
> need this to properly free the unused arrays. Calling devm_kfree() on a
> non-devres resource triggers a WARN_ON() for each call.
>
> Because of this I prepared a new version where the duplicated lists are
> freed after all the mod clocks were initialized. I'll publish it soon.

What about using in rzg2l_cpg_update_shared_mstop_clocks():

    for (i = 0; i < priv->num_mod_clks; i++) {
        clk = ...[i];

        if (clk->mstop != clock->mstop)
                continue;

        n = clk->num_shared_mstop_clks;
        if (!n) {
            new_clks = devm_kmalloc(dev, 2 * sizeof(...), GFP_KERNEL);
            new_clks[n++] = clk;
        } else {
            new_clks = devm_krealloc(dev, clk->shared_mstop_clks,
                                     (n + 1) * sizeof(...), GFP_KERNEL);
        }
        new_clks[n++] = clock;

        /* update all matching clocks */
        for (j = 0; j < n; j++) {
            priv->clks[new_clks[j]]->shared_mstop_clks = new_clks;
            priv->clks[new_clks[j]]->num_shared_mstop_clks = n;
        }

        break;
    }

The above is an oversimplification, as it does not take care of
converting between mstp_clock and clk_hw pointers where needed.

Does that make sense?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Powered by blists - more mailing lists