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Message-ID: <20250514150102.GA2180131-robh@kernel.org>
Date: Wed, 14 May 2025 10:01:02 -0500
From: Rob Herring <robh@...nel.org>
To: Ben Zong-You Xie <ben717@...estech.com>
Cc: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu,
alex@...ti.fr, krzk+dt@...nel.org, conor+dt@...nel.org,
tglx@...utronix.de, daniel.lezcano@...aro.org,
prabhakar.mahadev-lad.rj@...renesas.com, geert+renesas@...der.be,
magnus.damm@...il.com, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
tim609@...estech.com, Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v4 4/9] dt-bindings: interrupt-controller: add Andes
machine-level software interrupt controller
On Wed, May 14, 2025 at 05:53:45PM +0800, Ben Zong-You Xie wrote:
> Add the DT binding documentation for Andes machine-level software
> interrupt controller.
>
> In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
> second time with all interrupt sources tied to zero as the software
> interrupt controller (PLICSW). PLICSW can generate machine-level software
> interrupts through programming its registers.
>
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> Signed-off-by: Ben Zong-You Xie <ben717@...estech.com>
> ---
> .../andestech,plicsw.yaml | 54 +++++++++++++++++++
> MAINTAINERS | 1 +
This won't apply for me due to MAINTAINERS conflict with this series. So
apply the bindings patches with the dts files.
Rob
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