linux-kernel - Re: [PATCH v4 5/9] dt-bindings: timer: add Andes machine timer

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Message-ID: <aCS05j9ZYqga6dIO@mai.linaro.org>
Date: Wed, 14 May 2025 17:21:10 +0200
From: Daniel Lezcano <daniel.lezcano@...aro.org>
To: Ben Zong-You Xie <ben717@...estech.com>
Cc: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu,
	alex@...ti.fr, robh@...nel.org, krzk+dt@...nel.org,
	conor+dt@...nel.org, tglx@...utronix.de,
	prabhakar.mahadev-lad.rj@...renesas.com, geert+renesas@...der.be,
	magnus.damm@...il.com, devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
	tim609@...estech.com, Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v4 5/9] dt-bindings: timer: add Andes machine timer

On Wed, May 14, 2025 at 05:53:46PM +0800, Ben Zong-You Xie wrote:
> Add the DT binding documentation for Andes machine timer.
> 
> The RISC-V architecture defines a machine timer that provides a real-time
> counter and generates timer interrupts. Andes machiner timer (PLMT0) is
> the implementation of the machine timer, and it contains memory-mapped
> registers (mtime and mtimecmp). This device supports up to 32 cores.
> 
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> Signed-off-by: Ben Zong-You Xie <ben717@...estech.com>
> ---

The patch does not apply on my tree due to conflict with other patches
of the series on the MAINTAINER file.

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