linux-kernel - [RFC PATCH v6 13/32] x86/apic: Simplify bitwise operations on apic bitmap

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20250514071803.209166-14-Neeraj.Upadhyay@amd.com>
Date: Wed, 14 May 2025 12:47:44 +0530
From: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
To: <linux-kernel@...r.kernel.org>
CC: <bp@...en8.de>, <tglx@...utronix.de>, <mingo@...hat.com>,
	<dave.hansen@...ux.intel.com>, <Thomas.Lendacky@....com>, <nikunj@....com>,
	<Santosh.Shukla@....com>, <Vasant.Hegde@....com>,
	<Suravee.Suthikulpanit@....com>, <David.Kaplan@....com>, <x86@...nel.org>,
	<hpa@...or.com>, <peterz@...radead.org>, <seanjc@...gle.com>,
	<pbonzini@...hat.com>, <kvm@...r.kernel.org>,
	<kirill.shutemov@...ux.intel.com>, <huibo.wang@....com>,
	<naveen.rao@....com>, <francescolavra.fl@...il.com>, <tiala@...rosoft.com>
Subject: [RFC PATCH v6 13/32] x86/apic: Simplify bitwise operations on apic bitmap

Use 'regs' as a contiguous linear bitmap in  apic_{set|
clear|test}_vector() while doing bitwise operations.
This makes the code simpler by eliminating the need to
determine the offset of the 32-bit register and the vector
bit location within that register prior to performing
bitwise operations.

This change results in slight increase in generated code size for
gcc-14.2.

* Without change

apic_set_vector:
89 f8             mov    eax,edi
83 e7 1f          and    edi,0x1f
c1 e8 05          shr    eax,0x5
c1 e0 04          shl    eax,0x4
48 01 c6          add    rsi,rax
f0 48 0f ab 3e    lock bts QWORD PTR [rsi],rdi
c3                ret

* With change

apic_set_vector:

89 f8             mov    eax,edi
c1 e8 05          shr    eax,0x5
8d 04 40          lea    eax,[rax+rax*2]
c1 e0 05          shl    eax,0x5
01 f8             add    eax,edi
89 c0             mov    eax,eax
f0 48 0f ab 3e    lock bts QWORD PTR [rsi],rax

Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
---
Changes since v5:

 - New change which is refactored from v5 into common code (apic.h).

 arch/x86/include/asm/apic.h | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index ea43e2f4c1c8..eddcd3c31fef 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -564,19 +564,28 @@ static __always_inline void apic_set_reg64(void *regs, unsigned int reg, u64 val
 	ap->regs64[reg / 8] = val;
 }
 
+static inline unsigned int get_vec_bit(unsigned int vec)
+{
+	/*
+	 * The registers are 32-bit wide and 16-byte aligned.
+	 * Compensate for the resulting bit number spacing.
+	 */
+	return vec + 96 * (vec / 32);
+}
+
 static inline void apic_clear_vector(unsigned int vec, void *bitmap)
 {
-	clear_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec));
+	clear_bit(get_vec_bit(vec), bitmap);
 }
 
 static inline void apic_set_vector(unsigned int vec, void *bitmap)
 {
-	set_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec));
+	set_bit(get_vec_bit(vec), bitmap);
 }
 
 static inline int apic_test_vector(unsigned int vec, void *bitmap)
 {
-	return test_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec));
+	return test_bit(get_vec_bit(vec), bitmap);
 }
 
 /*
-- 
2.34.1