linux-kernel - Re: [RFC PATCH v2 4/6] x86/boot: Set 5-level paging CPU cap before entering C code

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Message-ID: <CAMj1kXF0Kc+--5rOqcVKoF-NhYfzA2rioaWsB09VK1hJ49nG+w@mail.gmail.com>
Date: Wed, 14 May 2025 09:18:24 +0100
From: Ard Biesheuvel <ardb@...nel.org>
To: Ingo Molnar <mingo@...nel.org>
Cc: Ard Biesheuvel <ardb+git@...gle.com>, linux-kernel@...r.kernel.org, x86@...nel.org, 
	Linus Torvalds <torvalds@...ux-foundation.org>
Subject: Re: [RFC PATCH v2 4/6] x86/boot: Set 5-level paging CPU cap before
 entering C code

On Wed, 14 May 2025 at 09:15, Ingo Molnar <mingo@...nel.org> wrote:
>
>
> * Ard Biesheuvel <ardb+git@...gle.com> wrote:
>
> > diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c
> > index ad4ea6fb3b6c..6259b474073b 100644
> > --- a/arch/x86/kernel/asm-offsets.c
> > +++ b/arch/x86/kernel/asm-offsets.c
> > @@ -33,6 +33,14 @@
> >
> >  static void __used common(void)
> >  {
> > +     OFFSET(CPUINFO_x86, cpuinfo_x86, x86);
> > +     OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
> > +     OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
> > +     OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping);
> > +     OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
> > +     OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
> > +     OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);
> > +
> >       BLANK();
> >       OFFSET(TASK_threadsp, task_struct, thread.sp);
> >  #ifdef CONFIG_STACKPROTECTOR
> > diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
> > index 2b411cd00a4e..e0a292db97b2 100644
> > --- a/arch/x86/kernel/asm-offsets_32.c
> > +++ b/arch/x86/kernel/asm-offsets_32.c
> > @@ -12,15 +12,6 @@ void foo(void);
> >
> >  void foo(void)
> >  {
> > -     OFFSET(CPUINFO_x86, cpuinfo_x86, x86);
> > -     OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
> > -     OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
> > -     OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping);
> > -     OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
> > -     OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
> > -     OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);
> > -     BLANK();
> > -
>
> This is needed so that we can run (well, build) the setup_force_cpu_cap
> macro on x86-64 too, right?
>
> Could you please split out this portion into a separate patch, to
> simplify the more dangerous half of the patch?
>

Sure.

> > -     if (IS_ENABLED(CONFIG_X86_5LEVEL) && (native_read_cr4() & X86_CR4_LA57))
> > -             setup_force_cpu_cap(X86_FEATURE_5LEVEL_PAGING);
>

Note that at this point, we'll likely still have to force clear the
original X86_FEATURE_LA57 bit, to address the issue that Kirill raised
that user space is now likely to conflate the "la57" cpuinfo string
with 5-level paging being in use.