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Message-Id: <107d4a6c1818bf169be2407b273a0483e6d55bbb.1747215274.git.namcao@linutronix.de>
Date: Wed, 14 May 2025 11:38:40 +0200
From: Nam Cao <namcao@...utronix.de>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Cc: Nam Cao <namcao@...utronix.de>,
Alexandre Ghiti <alexghiti@...osinc.com>
Subject: [PATCH v2 01/11] riscv: kprobes: Move branch_rs2_idx to insn.h
Similar to other instruction-processing macros/functions, branch_rs2_idx
should be in insn.h.
Move it into insn.h as RV_EXTRACT_RS2_REG. This new name matches the style
in insn.h.
Reviewed-by: Alexandre Ghiti <alexghiti@...osinc.com>
Signed-off-by: Nam Cao <namcao@...utronix.de>
---
arch/riscv/include/asm/insn.h | 5 +++++
arch/riscv/kernel/probes/simulate-insn.c | 5 +----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index 7c65fc8baeed..4a26cef3b5c0 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -64,6 +64,7 @@
#define RVG_RS2_OPOFF 20
#define RVG_RD_OPOFF 7
#define RVG_RS1_MASK GENMASK(4, 0)
+#define RVG_RS2_MASK GENMASK(4, 0)
#define RVG_RD_MASK GENMASK(4, 0)
/* The bit field of immediate value in RVC J instruction */
@@ -450,6 +451,10 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
({typeof(x) x_ = (x); \
(RV_X_mask(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
+#define RV_EXTRACT_RS2_REG(x) \
+ ({typeof(x) x_ = (x); \
+ (RV_X_mask(x_, RVG_RS2_OPOFF, RVG_RS2_MASK)); })
+
#define RV_EXTRACT_RD_REG(x) \
({typeof(x) x_ = (x); \
(RV_X_mask(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
diff --git a/arch/riscv/kernel/probes/simulate-insn.c b/arch/riscv/kernel/probes/simulate-insn.c
index 6c166029079c..77be381bb8b4 100644
--- a/arch/riscv/kernel/probes/simulate-insn.c
+++ b/arch/riscv/kernel/probes/simulate-insn.c
@@ -121,9 +121,6 @@ bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *re
#define branch_rs1_idx(opcode) \
(((opcode) >> 15) & 0x1f)
-#define branch_rs2_idx(opcode) \
- (((opcode) >> 20) & 0x1f)
-
#define branch_funct3(opcode) \
(((opcode) >> 12) & 0x7)
@@ -157,7 +154,7 @@ bool __kprobes simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *r
unsigned long rs2_val;
if (!rv_insn_reg_get_val(regs, branch_rs1_idx(opcode), &rs1_val) ||
- !rv_insn_reg_get_val(regs, branch_rs2_idx(opcode), &rs2_val))
+ !rv_insn_reg_get_val(regs, RV_EXTRACT_RS2_REG(opcode), &rs2_val))
return false;
offset_tmp = branch_offset(opcode);
--
2.39.5
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