linux-kernel - [PATCH v9 01/10] dt-bindings: serial: Added secondary clock for RZ/T2H RSCI

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-ID: <20250515141828.43444-2-thierry.bultel.yh@bp.renesas.com>
Date: Thu, 15 May 2025 16:18:16 +0200
From: Thierry Bultel <thierry.bultel.yh@...renesas.com>
To: thierry.bultel@...atsea.fr
Cc: linux-renesas-soc@...r.kernel.org,
	geert@...ux-m68k.org,
	paul.barker.ct@...renesas.com,
	Thierry Bultel <thierry.bultel.yh@...renesas.com>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	linux-kernel@...r.kernel.org,
	linux-serial@...r.kernel.org,
	devicetree@...r.kernel.org
Subject: [PATCH v9 01/10] dt-bindings: serial: Added secondary clock for RZ/T2H RSCI

At boot, the default clock is the PCLKM core clock (synchronous
clock, which is enabled by the bootloader).
For different baudrates, the asynchronous clock input must be used.
Clock selection is made by an internal register of RCSI.

Also remove the unneeded serial0 alias from the dts example.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
---
Changes v8->v9:
 - typo in description
 - named clocks 'operational' and 'bus', and added optional 'sck' clock
 - uses value of 2nd core clock in example to break the dependency on cpg patch
---
 .../bindings/serial/renesas,rsci.yaml         | 21 +++++++++++--------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
index ea879db5f485..e966d2b5f16d 100644
--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
@@ -35,10 +35,17 @@ properties:
       - const: tei
 
   clocks:
-    maxItems: 1
+    minItems: 2
+    maxItems: 3
 
   clock-names:
-    const: fck # UART functional clock
+    minItems: 2
+    maxItems: 3
+    items:
+      enum:
+        - operation
+        - bus
+        - sck # optional external clock input
 
   power-domains:
     maxItems: 1
@@ -58,11 +65,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
-    #include <dt-bindings/clock/renesas-cpg-mssr.h>
-
-    aliases {
-        serial0 = &sci0;
-    };
+    #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
 
     sci0: serial@...05000 {
         compatible = "renesas,r9a09g077-rsci";
@@ -72,7 +75,7 @@ examples:
                      <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
         interrupt-names = "eri", "rxi", "txi", "tei";
-        clocks = <&cpg CPG_MOD 108>;
-        clock-names = "fck";
+        clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE 13>;
+        clock-names = "operation", "bus";
         power-domains = <&cpg>;
     };
-- 
2.43.0