linux-kernel - Re: [PATCH v3 4/4] riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader

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Message-ID: <CAJM55Z8sqZ8g1zbphoKaqkZfFoh6GGCXF9dVPds5FydY3=46Gg@mail.gmail.com>
Date: Thu, 15 May 2025 10:10:05 -0700
From: Emil Renner Berthing <emil.renner.berthing@...onical.com>
To: E Shattow <e@...eshell.de>, Emil Renner Berthing <kernel@...il.dk>, Conor Dooley <conor@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, 
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v3 4/4] riscv: dts: starfive: jh7110-common:
 bootph-pre-ram hinting needed by boot loader

E Shattow wrote:
> Add bootph-pre-ram hinting to jh7110-common.dtsi:
>   - i2c5_pins and i2c-pins subnode for connection to eeprom
>   - eeprom node
>   - qspi flash configuration subnode
>   - memory node
>   - mmc0 for eMMC
>   - mmc1 for SD Card
>   - uart0 for serial console
>
>   With this the U-Boot SPL secondary program loader may drop such overrides.
>
> Signed-off-by: E Shattow <e@...eshell.de>

Acked-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>

> ---
>  arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index f1dc45b98e1d..d2cdb2f276c3 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -28,6 +28,7 @@ chosen {
>  	memory@...00000 {
>  		device_type = "memory";
>  		reg = <0x0 0x40000000 0x1 0x0>;
> +		bootph-pre-ram;
>  	};
>
>  	gpio-restart {
> @@ -249,6 +250,7 @@ emmc_vdd: aldo4 {
>  	eeprom@50 {
>  		compatible = "atmel,24c04";
>  		reg = <0x50>;
> +		bootph-pre-ram;
>  		pagesize = <16>;
>  	};
>  };
> @@ -268,6 +270,7 @@ &mmc0 {
>  	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
>  	assigned-clock-rates = <50000000>;
>  	bus-width = <8>;
> +	bootph-pre-ram;
>  	cap-mmc-highspeed;
>  	mmc-ddr-1_8v;
>  	mmc-hs200-1_8v;
> @@ -285,6 +288,7 @@ &mmc1 {
>  	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
>  	assigned-clock-rates = <50000000>;
>  	bus-width = <4>;
> +	bootph-pre-ram;
>  	no-sdio;
>  	no-mmc;
>  	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> @@ -323,6 +327,7 @@ &qspi {
>  	nor_flash: flash@0 {
>  		compatible = "jedec,spi-nor";
>  		reg = <0>;
> +		bootph-pre-ram;
>  		cdns,read-delay = <2>;
>  		spi-max-frequency = <100000000>;
>  		cdns,tshsl-ns = <1>;
> @@ -402,6 +407,8 @@ GPOEN_SYS_I2C2_DATA,
>  	};
>
>  	i2c5_pins: i2c5-0 {
> +		bootph-pre-ram;
> +
>  		i2c-pins {
>  			pinmux = <GPIOMUX(19, GPOUT_LOW,
>  					      GPOEN_SYS_I2C5_CLK,
> @@ -410,6 +417,7 @@ GPI_SYS_I2C5_CLK)>,
>  					      GPOEN_SYS_I2C5_DATA,
>  					      GPI_SYS_I2C5_DATA)>;
>  			bias-disable; /* external pull-up */
> +			bootph-pre-ram;
>  			input-enable;
>  			input-schmitt-enable;
>  		};
> @@ -638,6 +646,7 @@ GPOEN_DISABLE,
>  };
>
>  &uart0 {
> +	bootph-pre-ram;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&uart0_pins>;
>  	status = "okay";
> --
> 2.49.0
>