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Message-ID: <bac13842-9d15-4664-a20d-4916abcdc3e7@linux.intel.com>
Date: Thu, 15 May 2025 13:37:49 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: Sean Christopherson <seanjc@...gle.com>,
Mingwei Zhang <mizhang@...gle.com>
Cc: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Namhyung Kim <namhyung@...nel.org>, Paolo Bonzini <pbonzini@...hat.com>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>, Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>, Liang@...gle.com,
Kan <kan.liang@...ux.intel.com>, "H. Peter Anvin" <hpa@...or.com>,
linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
kvm@...r.kernel.org, linux-kselftest@...r.kernel.org,
Yongwei Ma <yongwei.ma@...el.com>,
Xiong Zhang <xiong.y.zhang@...ux.intel.com>,
Jim Mattson <jmattson@...gle.com>, Sandipan Das <sandipan.das@....com>,
Zide Chen <zide.chen@...el.com>, Eranian Stephane <eranian@...gle.com>,
Shukla Manali <Manali.Shukla@....com>,
Nikunj Dadhania <nikunj.dadhania@....com>
Subject: Re: [PATCH v4 23/38] KVM: x86/pmu: Configure the interception of PMU
MSRs
On 5/15/2025 8:41 AM, Sean Christopherson wrote:
> Again, use more precise language. "Configure interceptions" is akin to "do work".
> It gives readers a vague idea of what's going on, but this
>
> KVM: x86/pmu: Disable interception of select PMU MSRs for mediated vPMUs
>
> is just as concise, and more descriptive.
Yes, absolutely. Thanks.
>
>> + /*
>> + * In mediated vPMU, intercept global PMU MSRs when guest PMU only owns
>> + * a subset of counters provided in HW or its version is less than 2.
>> + */
>> + if (kvm_mediated_pmu_enabled(vcpu) && kvm_pmu_has_perf_global_ctrl(pmu) &&
>> + pmu->nr_arch_gp_counters == kvm_pmu_cap.num_counters_gp)
> This logic belongs in common code. Just because AMD doesn't have fixed counters
> doesn't mean KVM can't have a superfluous "0 == 0" check.
Yes.
>
>> + if (kvm_mediated_pmu_enabled(vcpu) && kvm_pmu_has_perf_global_ctrl(pmu) &&
> Just require the guest to have PERF_GLOBAL_CTRL, I don't see any reason to support
> v1 PMUs. It adds complexity and weirdness, and I can't imagine there's a use case.
Ok.
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