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Message-ID: <CY5PR11MB6366AACB5EA494893CA8D16DED90A@CY5PR11MB6366.namprd11.prod.outlook.com>
Date: Thu, 15 May 2025 11:23:38 +0000
From: "Usyskin, Alexander" <alexander.usyskin@...el.com>
To: "Jadav, Raag" <raag.jadav@...el.com>
CC: Miquel Raynal <miquel.raynal@...tlin.com>, Richard Weinberger
<richard@....at>, Vignesh Raghavendra <vigneshr@...com>, "De Marchi, Lucas"
<lucas.demarchi@...el.com>, Thomas Hellström
<thomas.hellstrom@...ux.intel.com>, "Vivi, Rodrigo" <rodrigo.vivi@...el.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard
<mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, David Airlie
<airlied@...il.com>, Simona Vetter <simona@...ll.ch>, Jani Nikula
<jani.nikula@...ux.intel.com>, Joonas Lahtinen
<joonas.lahtinen@...ux.intel.com>, Tvrtko Ursulin <tursulin@...ulin.net>,
"Poosa, Karthik" <karthik.poosa@...el.com>, "Abliyev, Reuven"
<reuven.abliyev@...el.com>, "Weil, Oren jer" <oren.jer.weil@...el.com>,
"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
"intel-xe@...ts.freedesktop.org" <intel-xe@...ts.freedesktop.org>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"intel-gfx@...ts.freedesktop.org" <intel-gfx@...ts.freedesktop.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Tomas Winkler
<tomasw@...il.com>
Subject: RE: [PATCH v9 03/12] mtd: intel-dg: implement region enumeration
> Subject: Re: [PATCH v9 03/12] mtd: intel-dg: implement region enumeration
>
> On Thu, Apr 24, 2025 at 04:25:27PM +0300, Alexander Usyskin wrote:
> > In intel-dg, there is no access to the spi controller,
> > the information is extracted from the descriptor region.
>
> ...
>
> > @@ -22,9 +24,199 @@ struct intel_dg_nvm {
> > u8 id;
> > u64 offset;
> > u64 size;
> > + unsigned int is_readable:1;
> > + unsigned int is_writable:1;
> > } regions[] __counted_by(nregions);
> > };
> >
> > +#define NVM_TRIGGER_REG 0x00000000
> > +#define NVM_VALSIG_REG 0x00000010
> > +#define NVM_ADDRESS_REG 0x00000040
> > +#define NVM_REGION_ID_REG 0x00000044
> > +/*
> > + * [15:0]-Erase size = 0x0010 4K 0x0080 32K 0x0100 64K
> > + * [23:16]-Reserved
> > + * [31:24]-Erase MEM RegionID
> > + */
> > +#define NVM_ERASE_REG 0x00000048
> > +#define NVM_ACCESS_ERROR_REG 0x00000070
> > +#define NVM_ADDRESS_ERROR_REG 0x00000074
> > +
> > +/* Flash Valid Signature */
> > +#define NVM_FLVALSIG 0x0FF0A55A
> > +
> > +#define NVM_MAP_ADDR_MASK GENMASK(7, 0)
> > +#define NVM_MAP_ADDR_SHIFT 0x00000004
> > +
> > +#define NVM_REGION_ID_DESCRIPTOR 0
> > +/* Flash Region Base Address */
> > +#define NVM_FRBA 0x40
> > +/* Flash Region __n - Flash Descriptor Record */
> > +#define NVM_FLREG(__n) (NVM_FRBA + ((__n) * 4))
> > +/* Flash Map 1 Register */
> > +#define NVM_FLMAP1_REG 0x18
> > +#define NVM_FLMSTR4_OFFSET 0x00C
> > +
> > +#define NVM_ACCESS_ERROR_PCIE_MASK 0x7
> > +
> > +#define NVM_FREG_BASE_MASK GENMASK(15, 0)
> > +#define NVM_FREG_ADDR_MASK GENMASK(31, 16)
> > +#define NVM_FREG_ADDR_SHIFT 12
> > +#define NVM_FREG_MIN_REGION_SIZE 0xFFF
>
> Should we move these to a header?
They are used only in this file, not shared to anyone, why to put in header?
>
> > +static inline void idg_nvm_set_region_id(struct intel_dg_nvm *nvm, u8
> region)
> > +{
> > + iowrite32((u32)region, nvm->base + NVM_REGION_ID_REG);
> > +}
> > +
> > +static inline u32 idg_nvm_error(struct intel_dg_nvm *nvm)
> > +{
> > + void __iomem *base = nvm->base;
> > +
> > + u32 reg = ioread32(base + NVM_ACCESS_ERROR_REG) &
> NVM_ACCESS_ERROR_PCIE_MASK;
> > +
> > + /* reset error bits */
> > + if (reg)
> > + iowrite32(reg, base + NVM_ACCESS_ERROR_REG);
> > +
> > + return reg;
> > +}
> > +
> > +static inline u32 idg_nvm_read32(struct intel_dg_nvm *nvm, u32 address)
> > +{
> > + void __iomem *base = nvm->base;
> > +
> > + iowrite32(address, base + NVM_ADDRESS_REG);
> > +
> > + return ioread32(base + NVM_TRIGGER_REG);
> > +}
> > +
> > +static int idg_nvm_get_access_map(struct intel_dg_nvm *nvm, u32
> *access_map)
> > +{
> > + u32 flmap1;
> > + u32 fmba;
> > + u32 fmstr4;
> > + u32 fmstr4_addr;
>
> Nit: These are in order of appearance vs reverse xmas tree in other places.
> Perhaps make them consistent?
Will do
>
> > + idg_nvm_set_region_id(nvm, NVM_REGION_ID_DESCRIPTOR);
> > +
> > + flmap1 = idg_nvm_read32(nvm, NVM_FLMAP1_REG);
> > + if (idg_nvm_error(nvm))
> > + return -EIO;
> > + /* Get Flash Master Baser Address (FMBA) */
> > + fmba = (FIELD_GET(NVM_MAP_ADDR_MASK, flmap1) <<
> NVM_MAP_ADDR_SHIFT);
> > + fmstr4_addr = fmba + NVM_FLMSTR4_OFFSET;
> > +
> > + fmstr4 = idg_nvm_read32(nvm, fmstr4_addr);
> > + if (idg_nvm_error(nvm))
> > + return -EIO;
> > +
> > + *access_map = fmstr4;
> > + return 0;
> > +}
> > +
> > +static bool idg_nvm_region_readable(u32 access_map, u8 region)
> > +{
> > + if (region < 12)
>
> Anything special about 12? Should it have a macro def somewhere?
>
The access bits are separated for first 12 regions and last 4.
My feeling that making below numbers #define will make
code less readable.
> > + return access_map & BIT(region + 8); /* [19:8] */
> > + else
> > + return access_map & BIT(region - 12); /* [3:0] */
> > +}
> > +
> > +static bool idg_nvm_region_writable(u32 access_map, u8 region)
> > +{
> > + if (region < 12)
>
> Ditto.
>
> > + return access_map & BIT(region + 20); /* [31:20] */
> > + else
> > + return access_map & BIT(region - 8); /* [7:4] */
> > +}
>
> Raag
- -
Thanks,
Sasha
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