linux-kernel - Re: [PATCH V3] arm64/mm: Re-organise setting up FEAT_S1PIE registers PIRE0_EL1 and PIR

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Message-Id: <174740439712.2574974.10617041555602541143.b4-ty@kernel.org>
Date: Fri, 16 May 2025 16:37:43 +0100
From: Will Deacon <will@...nel.org>
To: linux-arm-kernel@...ts.infradead.org,
	Anshuman Khandual <anshuman.khandual@....com>
Cc: catalin.marinas@....com,
	kernel-team@...roid.com,
	Will Deacon <will@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	Ard Biesheuvel <ardb@...nel.org>,
	Ryan Roberts <ryan.roberts@....com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH V3] arm64/mm: Re-organise setting up FEAT_S1PIE registers PIRE0_EL1 and PIR_EL1

On Tue, 29 Apr 2025 10:35:11 +0530, Anshuman Khandual wrote:
> mov_q cannot really move PIE_E[0|1] macros into a general purpose register
> as expected if those macro constants contain some 128 bit layout elements,
> that are required for D128 page tables. The primary issue is that for D128,
> PIE_E[0|1] are defined in terms of 128-bit types with shifting and masking,
> which the assembler can't accommodate.
> 
> Instead pre-calculate these PIRE0_EL1/PIR_EL1 constants into asm-offsets.h
> based PIE_E0_ASM/PIE_E1_ASM which can then be used in arch/arm64/mm/proc.S.
> 
> [...]

Applied to arm64 (for-next/entry), thanks!

[1/1] arm64/mm: Re-organise setting up FEAT_S1PIE registers PIRE0_EL1 and PIR_EL1
      https://git.kernel.org/arm64/c/29e31da4ed26

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev