linux-kernel - Re: [PATCH 2/2] spi: spi-qpic-snand: extend FIELD

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <9bb380f9-ba7f-8c6c-bf57-bb84eb96302f@quicinc.com>
Date: Fri, 16 May 2025 13:50:50 +0530
From: Md Sadre Alam <quic_mdalam@...cinc.com>
To: Gabor Juhos <j4g8y7@...il.com>, Mark Brown <broonie@...nel.org>
CC: Varadarajan Narayanan <quic_varada@...cinc.com>,
        Sricharan Ramabadhran
	<quic_srichara@...cinc.com>,
        <linux-spi@...r.kernel.org>, <linux-mtd@...ts.infradead.org>,
        <linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] spi: spi-qpic-snand: extend FIELD_PREP() macro usage



On 5/16/2025 12:28 AM, Gabor Juhos wrote:
> Large part of the code uses the FIELD_PREP() macro already to construct
> values to be written to hardware registers. Change the code to use also
> the macro for more registers of which the corresponding bitmasks are
> defined already.
> 
> This makes the code more readable. It also syncs the affected
> codes with their counterparts in the 'qcom_nandc' driver, so it
> makes it easier to spot the differences between the two
> implementations.
> 
> No functional changes intended.
> 
> Signed-off-by: Gabor Juhos <j4g8y7@...il.com>
> ---
>   drivers/spi/spi-qpic-snand.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
> index bc45b834fadc5456eda1fe778e5ca8b16177465e..ad01bb456a88b54f0ffc801dd14eb3fa2708ec2e 100644
> --- a/drivers/spi/spi-qpic-snand.c
> +++ b/drivers/spi/spi-qpic-snand.c
> @@ -130,9 +130,9 @@ static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
>   					int is_last_read_loc)
>   {
>   	__le32 locreg_val;
> -	u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
> -		  ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
> -		  << READ_LOCATION_LAST));
> +	u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
> +		  FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
> +		  FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
>   
>   	locreg_val = cpu_to_le32(val);
>   
> @@ -151,9 +151,9 @@ static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
>   				       int is_last_read_loc)
>   {
>   	__le32 locreg_val;
> -	u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
> -		  ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
> -		  << READ_LOCATION_LAST));
> +	u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
> +		  FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
> +		  FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
>   
>   	locreg_val = cpu_to_le32(val);
>   
> @@ -352,7 +352,7 @@ static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
>   			       FIELD_PREP(ECC_MODE_MASK, 0) |
>   			       FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
>   
> -	ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
> +	ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203);
>   	ecc_cfg->clrflashstatus = FS_READY_BSY_N;
>   	ecc_cfg->clrreadstatus = 0xc0;
>   
> 

Reviewed-by: Md Sadre Alam <quic_mdalam@...cinc.com>