linux-kernel - Re: [PATCH v10 03/13] x86/msr-index: define AMD heterogeneous CPU related MSR

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Message-ID: <aCb7f4ziOffNRrkd@gmail.com>
Date: Fri, 16 May 2025 10:46:55 +0200
From: Ingo Molnar <mingo@...nel.org>
To: Mario Limonciello <superm1@...nel.org>
Cc: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
	Mario Limonciello <mario.limonciello@....com>,
	Perry Yuan <perry.yuan@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
	"H . Peter Anvin" <hpa@...or.com>, Jonathan Corbet <corbet@....net>,
	Huang Rui <ray.huang@....com>,
	"Gautham R . Shenoy" <gautham.shenoy@....com>,
	"Rafael J . Wysocki" <rafael@...nel.org>,
	Viresh Kumar <viresh.kumar@...aro.org>,
	"open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER" <platform-driver-x86@...r.kernel.org>,
	"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <linux-kernel@...r.kernel.org>,
	"open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
	"open list:AMD PSTATE DRIVER" <linux-pm@...r.kernel.org>
Subject: Re: [PATCH v10 03/13] x86/msr-index: define AMD heterogeneous CPU
 related MSR


* Mario Limonciello <superm1@...nel.org> wrote:

> From: Perry Yuan <perry.yuan@....com>
> 
> Introduces new MSR registers for AMD hardware feedback support.
> These registers enable the system to provide workload classification
> and configuration capabilities.
> 
> Reviewed-by: Gautham R. Shenoy <gautham.shenoy@....com>
> Signed-off-by: Perry Yuan <perry.yuan@....com>
> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
>  arch/x86/include/asm/msr-index.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index b7dded3c81132..8e6db9a9f53c0 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -732,6 +732,11 @@
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302
>  
> +/* AMD Hardware Feedback Support MSRs */
> +#define AMD_WORKLOAD_CLASS_CONFIG      0xc0000500
> +#define AMD_WORKLOAD_CLASS_ID          0xc0000501
> +#define AMD_WORKLOAD_HRST              0xc0000502

Can we follow the existing pattern of MSR_AMD64_* or MSR_AMD_* that 99% 
of the indices in this header are following?

Thanks,

	Ingo