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Message-ID: <f5e1510f-3496-4f5e-b093-623d3b4be428@oss.qualcomm.com>
Date: Fri, 16 May 2025 11:00:46 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Neil Armstrong <neil.armstrong@...aro.org>,
Mrinmay Sarkar <mrinmay.sarkar@....qualcomm.com>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
krishna.chundru@....qualcomm.com, quic_vbadigan@...cinc.com,
quic_nayiluri@...cinc.com, quic_ramkri@...cinc.com,
quic_nitegupt@...cinc.com, Mrinmay Sarkar <quic_msarkar@...cinc.com>
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: sa8775p: Remove max link speed
property for PCIe EP
On 5/14/25 6:38 PM, neil.armstrong@...aro.org wrote:
> On 14/05/2025 13:37, Mrinmay Sarkar wrote:
>> From: Mrinmay Sarkar <mrinmay.sarkar@....qualcomm.com>
>>
>> The maximum link speed was previously restricted to Gen3 due to the
>> absence of Gen4 equalization support in the driver.
>>
>> Add change to remove max link speed property, Since Gen4 equalization
>> support has already been added into the driver.
>
> Which driver, PHY or Controller ?
Controller, see
09483959e34d ("PCI: dwc: Add support for configuring lane equalization presets")
and commits around it
does this change depends on the patch 1 PHY settings update ?
That I'm curious about too, but I would guesstimate no
Konrad
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