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Message-ID:
<DS7PR19MB88834246DF8B6F50CBDF64869D93A@DS7PR19MB8883.namprd19.prod.outlook.com>
Date: Fri, 16 May 2025 16:40:36 +0400
From: George Moussalem <george.moussalem@...look.com>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Luo Jie <quic_luoj@...cinc.com>,
Lee Jones <lee@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>,
Arnd Bergmann <arnd@...db.de>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v3 0/5] Add CMN PLL clock controller support for IPQ5018
Apologies, please disregard this version, something went wrong with
rebasing. I've sent version 4 in the meantime.
On 5/16/25 15:43, George Moussalem via B4 Relay wrote:
> The CMN PLL block of IPQ5018 supplies output clocks for XO at 24 MHZ,
> sleep at 32KHZ, and the ethernet block at 50MHZ.
>
> This patch series extends the CMN PLL driver to support IPQ5018. It also
> adds the SoC specific header file to export the CMN PLL output clock
> specifiers for IPQ5018. A new table of output clocks is added for the
> CMN PLL of IPQ5018, which is acquired from the device according to the
> compatible.
>
> Signed-off-by: George Moussalem <george.moussalem@...look.com>
> ---
> Changes in v3:
> - After further testing and evaluating different solutions, reverted to
> marking the XO clock in the GCC as critical as agreed with Konrad
> - Moved kernel traces out of commit message of patch 1 to under the
> diffstat separator and updated commit message accordingly
> - Updated commit message of patch 3
> - Link to v2: https://lore.kernel.org/r/20250506-ipq5018-cmn-pll-v2-0-c0a9fcced114@outlook.com
>
> Changes in v2:
> - Moved up commit documenting ipq5018 in qcom,tcsr bindings
> - Fixed binding issues reported by Rob's bot
> - Undone accidental deletion of reg property in cmn pll bindings
> - Fixed register address and size based on address and size cells of 1
> - Removed XO and XO_SRC clock structs from GCC and enabled them as
> always-on as suggested by Konrad
> - Removed bindings for XO and XO_SRC clocks
> - Removed qcom,tscr-cmn-pll-eth-enable property from bindings and will
> move logic to ipq5018 internal phy driver as per Jie's recommendation.
> - Removed addition of tcsr node and its bindings from this patch set
> - Corrected spelling mistakes
> - Link to v1: https://lore.kernel.org/r/20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com
>
> ---
> George Moussalem (5):
> clk: qcom: ipq5018: keep XO clock always on
> dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
> clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support
> arm64: dts: ipq5018: Add CMN PLL node
> arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock
>
> .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
> arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 3 +-
> .../dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 3 +-
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 20 ++++++++++--
> drivers/clk/qcom/gcc-ipq5018.c | 2 +-
> drivers/clk/qcom/ipq-cmn-pll.c | 37 ++++++++++++++--------
> include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h | 16 ++++++++++
> 7 files changed, 63 insertions(+), 19 deletions(-)
> ---
> base-commit: 8a2d53ce3c5f82683ad3df9a9a55822816fe64e7
> change-id: 20250501-ipq5018-cmn-pll-8e517de873f8
> prerequisite-change-id: 20250411-qcom_ipq5424_cmnpll-960a8f597033:v2
> prerequisite-patch-id: dc3949e10baf58f8c28d24bb3ffd347a78a1a2ee
> prerequisite-patch-id: da645619780de3186a3cccf25beedd4fefab36df
> prerequisite-patch-id: 4b5d81954f1f43d450a775bcabc1a18429933aaa
> prerequisite-patch-id: 541f835fb279f83e6eb2405c531bd7da9aacf4bd
>
> Best regards,
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