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Message-ID: <a18f1992-97de-4f29-8178-939e39cf43df@linaro.org>
Date: Sat, 17 May 2025 13:07:58 +0100
From: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
To: Wenmeng Liu <quic_wenmliu@...cinc.com>, rfoss@...nel.org,
todor.too@...il.com, andersson@...nel.org, konradybcio@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-media@...r.kernel.org,
quic_depengs@...cinc.com
Subject: Re: [PATCH RESEND] arm64: dts: qcom: sm8550: Add support for camss
On 16/05/2025 08:27, Wenmeng Liu wrote:
> Add support for the camera subsystem on the SM8550 Qualcomm SoC. This
> includes bringing up the CSIPHY, CSID, VFE/RDI interfaces.
>
> SM8550 provides
> - 3 x VFE, 3 RDI per VFE
> - 2 x VFE Lite, 4 RDI per VFE
> - 3 x CSID
> - 2 x CSID Lite
> - 8 x CSI PHY
>
> Co-developed-by: Depeng Shao <quic_depengs@...cinc.com>
> Signed-off-by: Depeng Shao <quic_depengs@...cinc.com>
> Signed-off-by: Wenmeng Liu <quic_wenmliu@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 210 +++++++++++++++++++++++++++
> 1 file changed, 210 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index e9bb077aa9f0..722521496a2d 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -3326,6 +3326,216 @@ cci2_i2c1: i2c-bus@1 {
> };
> };
>
> + isp: isp@...7000 {
> + compatible = "qcom,sm8550-camss";
> +
> + reg = <0x0 0x0acb7000 0x0 0x0d00>,
> + <0x0 0x0acb9000 0x0 0x0d00>,
> + <0x0 0x0acbb000 0x0 0x0d00>,
> + <0x0 0x0acca000 0x0 0x0a00>,
> + <0x0 0x0acce000 0x0 0x0a00>,
> + <0x0 0x0acb6000 0x0 0x1000>,
> + <0x0 0x0ace4000 0x0 0x2000>,
> + <0x0 0x0ace6000 0x0 0x2000>,
> + <0x0 0x0ace8000 0x0 0x2000>,
> + <0x0 0x0acea000 0x0 0x2000>,
> + <0x0 0x0acec000 0x0 0x2000>,
> + <0x0 0x0acee000 0x0 0x2000>,
> + <0x0 0x0acf0000 0x0 0x2000>,
> + <0x0 0x0acf2000 0x0 0x2000>,
> + <0x0 0x0ac62000 0x0 0xf000>,
> + <0x0 0x0ac71000 0x0 0xf000>,
> + <0x0 0x0ac80000 0x0 0xf000>,
> + <0x0 0x0accb000 0x0 0x1800>,
> + <0x0 0x0accf000 0x0 0x1800>;
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csid_wrapper",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "csiphy6",
> + "csiphy7",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_0_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_1_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_2_CLK>,
> + <&camcc CAM_CC_CSID_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY3_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY4_CLK>,
> + <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY5_CLK>,
> + <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY6_CLK>,
> + <&camcc CAM_CC_CSI6PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY7_CLK>,
> + <&camcc CAM_CC_CSI7PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_2_CLK>,
> + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "cpas_fast_ahb_clk",
> + "cpas_ife_lite",
> + "cpas_vfe0",
> + "cpas_vfe1",
> + "cpas_vfe2",
> + "csid",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "csiphy5",
> + "csiphy5_timer",
> + "csiphy6",
> + "csiphy6_timer",
> + "csiphy7",
> + "csiphy7_timer",
> + "csiphy_rx",
> + "gcc_axi_hf",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe2",
> + "vfe2_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid";
> +
> + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "csiphy6",
> + "csiphy7",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_0_mnoc";
> +
> + iommus = <&apps_smmu 0x800 0x20>;
> +
> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> + <&camcc CAM_CC_IFE_1_GDSC>,
> + <&camcc CAM_CC_IFE_2_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + power-domain-names = "ife0",
> + "ife1",
> + "ife2",
> + "top";
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + };
> +
> + port@3 {
> + reg = <3>;
> + };
> +
> + port@4 {
> + reg = <4>;
> + };
> +
> + port@5 {
> + reg = <5>;
> + };
> +
> + port@6 {
> + reg = <6>;
> + };
> +
> + port@7 {
> + reg = <7>;
> + };
> + };
> + };
> +
> camcc: clock-controller@...0000 {
> compatible = "qcom,sm8550-camcc";
> reg = <0 0x0ade0000 0 0x20000>;
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
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