linux-kernel - Re: [PATCH RFT v3 13/14] soc: qcom: ubwc: Fill in UBWC swizzle cfg for platforms that lack one

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Message-ID: <k57pmwohvnubbsxjxc7y74nkuayiktcrolbqlm5vorayrifemw@uuou33ffwdlb>
Date: Sun, 18 May 2025 12:59:45 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Konrad Dybcio <konradybcio@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>, Rob Clark <robdclark@...il.com>,
        Abhinav Kumar <quic_abhinavk@...cinc.com>,
        Akhil P Oommen <quic_akhilpo@...cinc.com>, Sean Paul <sean@...rly.run>,
        David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
        Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH RFT v3 13/14] soc: qcom: ubwc: Fill in UBWC swizzle cfg
 for platforms that lack one

On Sat, May 17, 2025 at 07:32:47PM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> 
> The UBWC 1.0 case is easy - it must be all 3 enabled.
> UBWC2.0 and 3.x require that level1 is removed, follow suit.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> ---
>  drivers/soc/qcom/ubwc_config.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)

Ideally we should test this on relevant platforms, the commit LGTM

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>

> 
> diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
> index fe874ccd8df6acb4fac65f7d261afb05861117c2..a4b730dac6c4aaa609d41b2782c9dc522387d8dd 100644
> --- a/drivers/soc/qcom/ubwc_config.c
> +++ b/drivers/soc/qcom/ubwc_config.c
> @@ -15,12 +15,18 @@
>  static const struct qcom_ubwc_cfg_data msm8937_data = {
>  	.ubwc_enc_version = UBWC_1_0,
>  	.ubwc_dec_version = UBWC_1_0,
> +	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
> +			UBWC_SWIZZLE_ENABLE_LVL2 |
> +			UBWC_SWIZZLE_ENABLE_LVL3,
>  	.highest_bank_bit = 14,
>  };
>  
>  static const struct qcom_ubwc_cfg_data msm8998_data = {
>  	.ubwc_enc_version = UBWC_1_0,
>  	.ubwc_dec_version = UBWC_1_0,
> +	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
> +			UBWC_SWIZZLE_ENABLE_LVL2 |
> +			UBWC_SWIZZLE_ENABLE_LVL3,
>  	.highest_bank_bit = 15,
>  };
>  
> @@ -70,6 +76,8 @@ static const struct qcom_ubwc_cfg_data sc7280_data = {
>  static const struct qcom_ubwc_cfg_data sc8180x_data = {
>  	.ubwc_enc_version = UBWC_3_0,
>  	.ubwc_dec_version = UBWC_3_0,
> +	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
> +			UBWC_SWIZZLE_ENABLE_LVL3,
>  	.highest_bank_bit = 16,
>  	.macrotile_mode = true,
>  };
> @@ -87,12 +95,16 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data = {
>  static const struct qcom_ubwc_cfg_data sdm670_data = {
>  	.ubwc_enc_version = UBWC_2_0,
>  	.ubwc_dec_version = UBWC_2_0,
> +	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
> +			UBWC_SWIZZLE_ENABLE_LVL3,
>  	.highest_bank_bit = 14,
>  };
>  
>  static const struct qcom_ubwc_cfg_data sdm845_data = {
>  	.ubwc_enc_version = UBWC_2_0,
>  	.ubwc_dec_version = UBWC_2_0,
> +	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
> +			UBWC_SWIZZLE_ENABLE_LVL3,
>  	.highest_bank_bit = 15,
>  };
>  
> @@ -118,6 +130,8 @@ static const struct qcom_ubwc_cfg_data sm6125_data = {
>  static const struct qcom_ubwc_cfg_data sm6150_data = {
>  	.ubwc_enc_version = UBWC_2_0,
>  	.ubwc_dec_version = UBWC_2_0,
> +	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
> +			UBWC_SWIZZLE_ENABLE_LVL3,
>  	.highest_bank_bit = 14,
>  };
>  
> @@ -133,12 +147,16 @@ static const struct qcom_ubwc_cfg_data sm6350_data = {
>  static const struct qcom_ubwc_cfg_data sm7150_data = {
>  	.ubwc_enc_version = UBWC_2_0,
>  	.ubwc_dec_version = UBWC_2_0,
> +	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
> +			UBWC_SWIZZLE_ENABLE_LVL3,
>  	.highest_bank_bit = 14,
>  };
>  
>  static const struct qcom_ubwc_cfg_data sm8150_data = {
>  	.ubwc_enc_version = UBWC_3_0,
>  	.ubwc_dec_version = UBWC_3_0,
> +	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
> +			UBWC_SWIZZLE_ENABLE_LVL3,
>  	.highest_bank_bit = 15,
>  };
>  
> 
> -- 
> 2.49.0
> 

-- 
With best wishes
Dmitry