| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20250518220449.2722673-3-heiko@sntech.de>
Date: Mon, 19 May 2025 00:04:44 +0200
From: Heiko Stuebner <heiko@...ech.de>
To: heiko@...ech.de
Cc: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
ziyao@...root.org,
kever.yang@...k-chips.com,
nicolas.frattaroli@...labora.com,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org,
kernel test robot <lkp@...el.com>
Subject: [PATCH 2/6] arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
as dtc points out:
../arch/arm64/boot/dts/rockchip/rk3576.dtsi:2351.20-2417.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property
Move the pinctrl node outside and adapt the indentation.
Reported-by: kernel test robot <lkp@...el.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/
Signed-off-by: Heiko Stuebner <heiko@...ech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 136 +++++++++++------------
1 file changed, 68 insertions(+), 68 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 3b62e037772a..0e0a37849874 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -429,6 +429,74 @@ simple-audio-card,cpu {
};
};
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3576-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@...20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x27320000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@...10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae10000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@...20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae20000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@...30000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae30000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@...40000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae40000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+ };
+
pmu_a53: pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@@ -2347,74 +2415,6 @@ scmi_shmem: scmi-shmem@...0f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x4010f000 0x0 0x100>;
};
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3576-pinctrl";
- rockchip,grf = <&ioc_grf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@...20000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x27320000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 32>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@...10000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae10000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 32 32>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@...20000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae20000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 64 32>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@...30000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae30000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 96 32>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@...40000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae40000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 128 32>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
- };
};
};
--
2.47.2
Powered by blists - more mailing lists