| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <mqf33f6bd6w7ozklh7igpa7ybgzuicqfxrbokvdcvcofwayffx@i6g5mqebahif>
Date: Sun, 18 May 2025 09:07:55 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: weishangjuan@...incomputing.com, andrew+netdev@...n.ch,
davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
richardcochran@...il.com, netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, mcoquelin.stm32@...il.com, alexandre.torgue@...s.st.com,
p.zabel@...gutronix.de, yong.liang.choong@...ux.intel.com, rmk+kernel@...linux.org.uk,
jszhang@...nel.org, inochiama@...il.com, jan.petrous@....nxp.com,
dfustini@...storrent.com, 0x1207@...il.com, linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org
Cc: ningyu@...incomputing.com, linmin@...incomputing.com,
lizhi2@...incomputing.com
Subject: Re: [PATCH v1 1/2] ethernet: eswin: Document for eic7700 SoC
On Fri, May 16, 2025 at 09:10:38AM +0800, weishangjuan@...incomputing.com wrote:
> From: Shangjuan Wei <weishangjuan@...incomputing.com>
>
> Add ESWIN EIC7700 Ethernet controller, supporting
> multi-rate (10M/100M/1G) auto-negotiation, PHY LED configuration,
> clock/reset control, and AXI bus parameter optimization.
>
> Signed-off-by: Zhi Li <lizhi2@...incomputing.com>
> Signed-off-by: Shangjuan Wei <weishangjuan@...incomputing.com>
> ---
> .../bindings/net/eswin,eic7700-eth.yaml | 142 ++++++++++++++++++
> 1 file changed, 142 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> new file mode 100644
> index 000000000000..6cb9c109c036
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> @@ -0,0 +1,142 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Eswin EIC7700 SOC Eth Controller
> +
> +maintainers:
> + - Shuang Liang <liangshuang@...incomputing.com>
> + - Zhi Li <lizhi2@...incomputing.com>
> + - Shangjuan Wei <weishangjuan@...incomputing.com>
> +
> +description: |
> + The eth controller registers are part of the syscrg block on
> + the EIC7700 SoC.
> +
> +properties:
> + compatible:
> + const: eswin,eic7700-qos-eth
Please set the related dwmac version as basic compatible,
it should be something like snps,dwmac-xxx.
> +
> + reg:
> + minItems: 1
> + items:
> + - description: Base address and size
> + - description: Extension region (optional)
> +
> + interrupt-names:
> + const: macirq
> +
> + interrupts:
> + maxItems: 1
> +
> + phy-mode:
> + $ref: /schemas/types.yaml#/definitions/string
> + enum: [mii, gmii, rgmii, rmii, sgmii]
> +
> + id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Controller instance ID
> +
> + clocks:
> + minItems: 3
> + maxItems: 7
> +
> + clock-names:
> + minItems: 3
> + items:
> + - const: app
> + - const: stmmaceth
> + - const: tx
> + - const: slave_bus
> + - const: master_bus
> + - const: ptp_ref
> + - const: phy_ref_clk
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + items:
> + - const: ethrst
Please refer to snps,dwmac.yaml and set a matching name.
This applies to all properties with snp prefix.
> +
> + dma-noncoherent: true
> +
> + # Custom properties
> + eswin,hsp_sp_csr:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: HSP SP control registers
> +
> + eswin,syscrg_csr:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: System clock registers
> +
> + eswin,dly_hsp_reg:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: HSP delay control registers
> +
> + snps,axi-config:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: AXI bus configuration
> +
> + stmmac-axi-config:
> + type: object
> + unevaluatedProperties: false
> + properties:
> + snps,lpi_en:
> + type: boolean
> + $ref: /schemas/types.yaml#/definitions/flag
> + description: Low Power Interface enable flag (true/false)
> +
> +required:
> + - compatible
> + - reg
> + - interrupt-names
> + - interrupts
> + - phy-mode
> + - id
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - eswin,hsp_sp_csr
> + - eswin,syscrg_csr
> + - eswin,dly_hsp_reg
> + - snps,axi-config
> + - snps,blen
> + - snps,rd_osr_lmt
> + - snps,wr_osr_lmt
> + - snps,lpi_en
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + gmac0: ethernet@...00000 {
> + compatible = "eswin,eic7700-qos-eth";
> + reg = <0x0 0x50400000 0x0 0x10000>;
> + interrupt-parent = <&plic>;
> + interrupt-names = "macirq";
> + interrupts = <61>;
> + phy-mode = "rgmii";
> + id = <0>;
> + status = "disabled";
> + clocks = <&clock 550>,
> + <&clock 551>,
> + <&clock 552>;
> + clock-names = "app", "stmmaceth", "tx";
> + resets = <&reset 0x07 (1 << 26)>;
> + reset-names = "ethrst";
> + dma-noncoherent;
> + eswin,hsp_sp_csr = <&hsp_sp_csr 0x1030 0x100 0x108>;
> + eswin,syscrg_csr = <&sys_crg 0x148 0x14c>;
> + eswin,dly_hsp_reg = <0x114 0x118 0x11c>;
> + snps,axi-config = <&stmmac_axi_setup>;
> + stmmac_axi_setup: stmmac-axi-config {
> + snps,blen = <0 0 0 0 16 8 4>;
> + snps,rd_osr_lmt = <2>;
> + snps,wr_osr_lmt = <2>;
> + snps,lpi_en;
> + };
> + };
> --
> 2.17.1
>
Powered by blists - more mailing lists