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Message-Id: <20250519163156.217567-3-18255117159@163.com>
Date: Tue, 20 May 2025 00:31:55 +0800
From: Hans Zhang <18255117159@....com>
To: bhelgaas@...gle.com,
lpieralisi@...nel.org,
kw@...ux.com,
krzk+dt@...nel.org,
manivannan.sadhasivam@...aro.org,
ilpo.jarvinen@...ux.intel.com,
jingoohan1@...il.com
Cc: robh@...nel.org,
linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org,
Hans Zhang <18255117159@....com>
Subject: [PATCH 2/3] PCI: dwc: Simplify link speed configuration with macro
Replace switch-case based speed-to-register conversion in DesignWare
driver with the newly introduced PCIE_SPEED2LNKCTL2_TLS_ENC macro.
Signed-off-by: Hans Zhang <18255117159@....com>
---
drivers/pci/controller/dwc/pcie-designware.c | 18 +++---------------
1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 97d76d3dc066..951e2ce69dfa 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -754,24 +754,12 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
- switch (pcie_link_speed[pci->max_link_speed]) {
- case PCIE_SPEED_2_5GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
- break;
- case PCIE_SPEED_5_0GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
- break;
- case PCIE_SPEED_8_0GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
- break;
- case PCIE_SPEED_16_0GT:
- link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
- break;
- default:
+ link_speed = pcie_link_speed[pci->max_link_speed];
+ link_speed = PCIE_SPEED2LNKCTL2_TLS_ENC(link_speed);
+ if (link_speed == 0) {
/* Use hardware capability */
link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
- break;
}
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
--
2.25.1
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