linux-kernel - Re: [PATCH 2/3] dt-bindings: arm: cpus: Add edac-enabled property

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Message-ID: <20250519090253.GGaCrzvRFC75JnFN1S@fat_crate.local>
Date: Mon, 19 May 2025 11:02:53 +0200
From: Borislav Petkov <bp@...en8.de>
To: Vijay Balakrishna <vijayb@...ux.microsoft.com>
Cc: Tony Luck <tony.luck@...el.com>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	James Morse <james.morse@....com>,
	Mauro Carvalho Chehab <mchehab@...nel.org>,
	Robert Richter <rric@...nel.org>, linux-edac@...r.kernel.org,
	linux-kernel@...r.kernel.org, Tyler Hicks <code@...icks.com>,
	Marc Zyngier <maz@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	devicetree@...r.kernel.org
Subject: Re: [PATCH 2/3] dt-bindings: arm: cpus: Add edac-enabled property

On Thu, May 15, 2025 at 05:06:12PM -0700, Vijay Balakrishna wrote:
> From: Sascha Hauer <s.hauer@...gutronix.de>
> 
> Some ARM Cortex CPUs including A72 have Error Detection And
> Correction (EDAC) support on their L1 and L2 caches. This is implemented
> in implementation defined registers, so usage of this functionality is
> not safe in virtualized environments or when EL3 already uses these
> registers. This patch adds a edac-enabled flag which can be explicitly
> set when EDAC can be used.
> 
> Signed-off-by: Sascha Hauer <s.hauer@...gutronix.de>
> [vijayb: Limit A72 in the commit message]
> Signed-off-by: Vijay Balakrishna <vijayb@...ux.microsoft.com>
> ---
>  Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)

This needs an Ack from DT maintainers.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette