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Message-ID: <20250518193152.63476-7-shradha.t@samsung.com>
Date: Mon, 19 May 2025 01:01:48 +0530
From: Shradha Todi <shradha.t@...sung.com>
To: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.or,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org
Cc: manivannan.sadhasivam@...aro.org, lpieralisi@...nel.org, kw@...ux.com,
robh@...nel.org, bhelgaas@...gle.com, jingoohan1@...il.com,
krzk+dt@...nel.org, conor+dt@...nel.org, alim.akhtar@...sung.com,
vkoul@...nel.org, kishon@...nel.org, arnd@...db.de,
m.szyprowski@...sung.com, jh80.chung@...sung.com, Shradha Todi
<shradha.t@...sung.com>
Subject: [PATCH 06/10] dt-bindings: PCI: Add bindings support for Tesla FSD
SoC
Document the PCIe controller device tree bindings for Tesla FSD
SoC for both RC and EP.
Signed-off-by: Shradha Todi <shradha.t@...sung.com>
---
.../bindings/pci/samsung,exynos-pcie-ep.yaml | 66 ++++++
.../bindings/pci/samsung,exynos-pcie.yaml | 199 ++++++++++++------
2 files changed, 198 insertions(+), 67 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie-ep.yaml
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie-ep.yaml
new file mode 100644
index 000000000000..5d4a9067f727
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie-ep.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series PCIe Endpoint Controller
+
+maintainers:
+ - Shradha Todi <shradha.t@...sung.co>
+
+description: |+
+ Samsung SoCs PCIe endpoint controller is based on the Synopsys DesignWare
+ PCIe IP and thus inherits all the common properties defined in
+ snps,dw-pcie-ep.yaml.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - tesla,fsd-pcie-ep
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - tesla,fsd-pcie-ep
+ then:
+ properties:
+ samsung,syscon-pcie:
+ description: phandle for system control registers, used to
+ control signals at system level
+
+ required:
+ - samsung,syscon-pcie
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/fsd-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcieep0: pcie-ep@...00000 {
+ compatible = "tesla,fsd-pcie-ep";
+ reg = <0x0 0x168b0000 0x0 0x1000>,
+ <0x0 0x16a00000 0x0 0x2000>,
+ <0x0 0x16a01000 0x0 0x80>,
+ <0x0 0x17000000 0x0 0xff0000>;
+ reg-names = "elbi", "dbi", "dbi2", "addr_space";
+ clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>;
+ clock-names = "aux", "dbi", "mstr", "slv";
+ num-lanes = <4>;
+ samsung,syscon-pcie = <&sysreg_fsys1 0x50c>;
+ phys = <&pciephy1>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
index f20ed7e709f7..a3803bf0ef84 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
@@ -11,78 +11,113 @@ maintainers:
- Jaehoon Chung <jh80.chung@...sung.com>
description: |+
- Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
+ Samsung SoCs PCIe host controller is based on the Synopsys DesignWare
PCIe IP and thus inherits all the common properties defined in
snps,dw-pcie.yaml.
-allOf:
- - $ref: /schemas/pci/snps,dw-pcie.yaml#
-
properties:
compatible:
- const: samsung,exynos5433-pcie
-
- reg:
- items:
- - description: Data Bus Interface (DBI) registers.
- - description: External Local Bus interface (ELBI) registers.
- - description: PCIe configuration space region.
-
- reg-names:
- items:
- - const: dbi
- - const: elbi
- - const: config
-
- interrupts:
- maxItems: 1
-
- clocks:
- items:
- - description: PCIe bridge clock
- - description: PCIe bus clock
-
- clock-names:
- items:
- - const: pcie
- - const: pcie_bus
-
- phys:
- maxItems: 1
-
- vdd10-supply:
- description:
- Phandle to a regulator that provides 1.0V power to the PCIe block.
-
- vdd18-supply:
- description:
- Phandle to a regulator that provides 1.8V power to the PCIe block.
-
- num-lanes:
- const: 1
-
- num-viewport:
- const: 3
-
-required:
- - reg
- - reg-names
- - interrupts
- - "#address-cells"
- - "#size-cells"
- - "#interrupt-cells"
- - interrupt-map
- - interrupt-map-mask
- - ranges
- - bus-range
- - device_type
- - num-lanes
- - num-viewport
- - clocks
- - clock-names
- - phys
- - vdd10-supply
- - vdd18-supply
+ oneOf:
+ - enum:
+ - samsung,exynos5433-pcie
+ - tesla,fsd-pcie
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - tesla,fsd-pcie
+ then:
+ properties:
+ samsung,syscon-pcie:
+ description: phandle for system control registers, used to
+ control signals at system level
+
+ required:
+ - samsung,syscon-pcie
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos5433-pcie
+ then:
+ properties:
+ reg:
+ items:
+ - description: controller's own configuration registers
+ are available.
+ - description: controller's application logic registers
+ - description: configuration registers
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: config
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: pcie bridge clock
+ - description: pcie bus clock
+
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+
+ phys:
+ maxItems: 1
+
+ vdd10-supply:
+ description:
+ phandle to a regulator that provides 1.0v power to the pcie block.
+
+ vdd18-supply:
+ description:
+ phandle to a regulator that provides 1.8v power to the pcie block.
+
+ num-lanes:
+ const: 1
+
+ num-viewport:
+ const: 3
+
+ assigned-clocks:
+ maxItems: 2
+
+ assigned-clock-parents:
+ maxItems: 2
+
+ assigned-clock-rates:
+ maxItems: 2
+
+ required:
+ - reg
+ - reg-names
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+ - "#interrupt-cells"
+ - interrupt-map
+ - interrupt-map-mask
+ - ranges
+ - bus-range
+ - device_type
+ - num-lanes
+ - num-viewport
+ - clocks
+ - clock-names
+ - phys
+ - vdd10-supply
+ - vdd18-supply
unevaluatedProperties: false
@@ -116,4 +151,34 @@ examples:
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
};
+ - |
+ #include <dt-bindings/clock/fsd-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcierc0: pcie@...00000 {
+ compatible = "tesla,fsd-pcie";
+ reg = <0x0 0x16a00000 0x0 0x2000>,
+ <0x0 0x168b0000 0x0 0x1000>,
+ <0x0 0x17000000 0x0 0x1000>;
+ reg-names = "dbi", "elbi", "config";
+ ranges = <0x82000000 0 0x17001000 0 0x17001000 0 0xffefff>;
+ clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>;
+ clock-names = "aux", "dbi", "mstr", "slv";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-coherent;
+ device_type = "pci";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>;
+ num-lanes = <4>;
+ samsung,syscon-pcie = <&sysreg_fsys1 0x50c>;
+ phys = <&pciephy1>;
+ iommu-map = <0x0 &smmu_imem 0x0 0x10000>;
+ iommu-map-mask = <0x0>;
+ };
+ };
...
--
2.49.0
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