linux-kernel - RE: [PATCH v5 2/5] x86/cpufeatures: Add X86_FEATURE_SGX

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <DM8PR11MB575081096D343262E17F53EBE79CA@DM8PR11MB5750.namprd11.prod.outlook.com>
Date: Mon, 19 May 2025 11:29:04 +0000
From: "Reshetova, Elena" <elena.reshetova@...el.com>
To: Ingo Molnar <mingo@...nel.org>
CC: "Hansen, Dave" <dave.hansen@...el.com>, "jarkko@...nel.org"
	<jarkko@...nel.org>, "seanjc@...gle.com" <seanjc@...gle.com>, "Huang, Kai"
	<kai.huang@...el.com>, "linux-sgx@...r.kernel.org"
	<linux-sgx@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "x86@...nel.org" <x86@...nel.org>, "Mallick,
 Asit K" <asit.k.mallick@...el.com>, "Scarlata, Vincent R"
	<vincent.r.scarlata@...el.com>, "Cai, Chong" <chongc@...gle.com>, "Aktas,
 Erdem" <erdemaktas@...gle.com>, "Annapurve, Vishal" <vannapurve@...gle.com>,
	"dionnaglaze@...gle.com" <dionnaglaze@...gle.com>, "bondarn@...gle.com"
	<bondarn@...gle.com>, "Raynor, Scott" <scott.raynor@...el.com>
Subject: RE: [PATCH v5 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN
 feature flag


> * Elena Reshetova <elena.reshetova@...el.com> wrote:
> 
> > Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction
> > is supported. This will be used by SGX driver to perform CPU
> > SVN updates.
> >
> > Signed-off-by: Elena Reshetova <elena.reshetova@...el.com>
> > ---
> >  arch/x86/include/asm/cpufeatures.h       | 1 +
> >  arch/x86/kernel/cpu/scattered.c          | 1 +
> >  tools/arch/x86/include/asm/cpufeatures.h | 1 +
> >  3 files changed, 3 insertions(+)
> >
> > diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> > index 6c2c152d8a67..ed0c0fa5822a 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -481,6 +481,7 @@
> >  #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /*
> Heterogeneous Core Topology */
> >  #define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /*
> Workload Classification */
> >  #define X86_FEATURE_PREFER_YMM		(21*32 + 8) /* Avoid ZMM
> registers due to downclocking */
> > +#define X86_FEATURE_SGX_EUPDATESVN	(21*32 + 9) /* Support for
> ENCLS[EUPDATESVN] instruction */
> 
> Please base the patches on the latest x86 tree, there's been two
> additions already in this area.

Will do in the next iteration.

> 
> >  /*
> >   * BUG word(s)
> > diff --git a/arch/x86/kernel/cpu/scattered.c
> b/arch/x86/kernel/cpu/scattered.c
> > index 16f3ca30626a..a7e1fcedca3c 100644
> > --- a/arch/x86/kernel/cpu/scattered.c
> > +++ b/arch/x86/kernel/cpu/scattered.c
> > @@ -41,6 +41,7 @@ static const struct cpuid_bit cpuid_bits[] = {
> >  	{ X86_FEATURE_PER_THREAD_MBA,		CPUID_ECX,  0,
> 0x00000010, 3 },
> >  	{ X86_FEATURE_SGX1,			CPUID_EAX,  0, 0x00000012, 0
> },
> >  	{ X86_FEATURE_SGX2,			CPUID_EAX,  1, 0x00000012, 0
> },
> > +	{ X86_FEATURE_SGX_EUPDATESVN,	CPUID_EAX, 10, 0x00000012,
> 0 },
> >  	{ X86_FEATURE_SGX_EDECCSSA,		CPUID_EAX, 11,
> 0x00000012, 0 },
> >  	{ X86_FEATURE_HW_PSTATE,		CPUID_EDX,  7, 0x80000007, 0
> },
> >  	{ X86_FEATURE_CPB,			CPUID_EDX,  9, 0x80000007, 0
> },
> 
> So it should be obvious at a glance that this new line doesn't follow
> the coding convention of the surrounding lines...

Will fix also.