linux-kernel - RE: [External] Re: [PATCH v3 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC

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Message-ID:
 <SA3PR04MB8931011F9B1C3B54ED3ED463839CA@SA3PR04MB8931.namprd04.prod.outlook.com>
Date: Mon, 19 May 2025 13:32:33 +0000
From: Pinkesh Vaghela <pinkesh.vaghela@...fochips.com>
To: Jisheng Zhang <jszhang@...nel.org>
CC: Conor Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof
 Kozlowski <krzk+dt@...nel.org>, Thomas Gleixner <tglx@...utronix.de>, Paul
 Walmsley <paul.walmsley@...ive.com>, Samuel Holland
	<samuel.holland@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou
	<aou@...s.berkeley.edu>, Daniel Lezcano <daniel.lezcano@...aro.org>, Min Lin
	<linmin@...incomputing.com>, Pritesh Patel <pritesh.patel@...fochips.com>,
	Yangyu Chen <cyy@...self.name>, Lad Prabhakar
	<prabhakar.mahadev-lad.rj@...renesas.com>, Yu Chien Peter Lin
	<peterlin@...estech.com>, Charlie Jenkins <charlie@...osinc.com>, Kanak
 Shilledar <kanakshilledar@...il.com>, Darshan Prajapati
	<darshan.prajapati@...fochips.com>, Neil Armstrong
	<neil.armstrong@...aro.org>, Heiko Stuebner <heiko@...ech.de>, Aradhya Bhatia
	<a-bhatia1@...com>, "rafal@...ecki.pl" <rafal@...ecki.pl>, Anup Patel
	<anup@...infault.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-riscv@...ts.infradead.org"
	<linux-riscv@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [External] Re: [PATCH v3 00/10] Basic device tree support for
 ESWIN EIC7700 RISC-V SoC

Hi Jisheng,

On Sat, Apr 26, 2025 at 08:03 PM, Jisheng Zhang wrote:
> On Thu, Apr 10, 2025 at 08:55:09PM +0530, Pinkesh Vaghela wrote:
> > Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core
> > P550 CPU cluster and the first development board that uses it, the
> > SiFive HiFive Premier P550.
> >
> > This patch series adds initial device tree and also adds ESWIN
> > architecture support.
> 
> Per past experience, new SoC needs at least pinctrl and clk tree ready.

Patches for pinctrl [1] and clk [2] are already posted.

[1] https://lore.kernel.org/lkml/20250515054524.390-1-luyulin@eswincomputing.com/
[2] https://lore.kernel.org/lkml/20250514002233.187-1-dongxuyang@eswincomputing.com/

Regards,
Pinkesh

> >
> > Boot-tested using intiramfs with Linux 6.15.0-rc1 on HiFive Premier
> > P550 board using U-Boot 2024.01 and OpenSBI 1.4.
> >
> > Changes in v3:
> > - Rebased the patches to kernel 6.15.0-rc1
> > - Added "Reviewed-by" tag of "Rob Herring" for Patch 4
> > - Updated MAINTAINERS file
> >   - Add GIT tree URL
> > - Updated DTSI file
> >   - Added "dma-noncoherent" property to soc node
> >   - Updated GPIO node labels in DTSI file
> > - Link to v2:
> > https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Flkml%2F20250320105449.2094192-1-
> pinkesh.vaghela%40einfoc
> >
> hips.com%2F&data=05%7C02%7Cpinkesh.vaghela%40einfochips.com%7Caf77
> b3ac
> >
> 71d1493ae0ed08dd84d189fd%7C0beb0c359cbb4feb99e5589e415c7944%7C1
> %7C0%7C
> >
> 638812757761987583%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOn
> RydWUsIlY
> >
> iOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%
> 7C0%
> >
> 7C%7C%7C&sdata=zD3XwzY2lc41amPRgFO%2Bz60qj68MC1Wf2Krr9G%2FEQ
> wM%3D&rese
> > rved=0
> >
> > Changes in v2:
> > - Added "Acked-by" tag of "Conor Dooley" for Patches 1, 2, 3, 7 and 8
> > - Added "Reviewed-by" tag of "Matthias Brugger" for Patch 4
> > - Updated MAINTAINERS file
> >   - Add the path for the eswin binding file
> > - Updated sifive,ccache0.yaml
> >   - Add restrictions for "cache-size" property based on the
> >     compatible string
> > - Link to v1:
> > https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Flkml%2F20250311073432.4068512-1-
> pinkesh.vaghela%40einfoc
> >
> hips.com%2F&data=05%7C02%7Cpinkesh.vaghela%40einfochips.com%7Caf77
> b3ac
> >
> 71d1493ae0ed08dd84d189fd%7C0beb0c359cbb4feb99e5589e415c7944%7C1
> %7C0%7C
> >
> 638812757762011608%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOn
> RydWUsIlY
> >
> iOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%
> 7C0%
> >
> 7C%7C%7C&sdata=MIU%2Fh9VO2VYnJ5VwixXO0zU1%2Fr4AsWif1wwX31VeS
> gw%3D&rese
> > rved=0
> >
> > Darshan Prajapati (3):
> >   dt-bindings: riscv: Add SiFive P550 CPU compatible
> >   dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC
> >   dt-bindings: timer: Add ESWIN EIC7700 CLINT
> >
> > Min Lin (2):
> >   riscv: dts: add initial support for EIC7700 SoC
> >   riscv: dts: eswin: add HiFive Premier P550 board device tree
> >
> > Pinkesh Vaghela (2):
> >   riscv: Add Kconfig option for ESWIN platforms
> >   cache: sifive_ccache: Add ESWIN EIC7700 support
> >
> > Pritesh Patel (3):
> >   dt-bindings: vendor-prefixes: add eswin
> >   dt-bindings: riscv: Add SiFive HiFive Premier P550 board
> >   dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC
> >     compatibility
> >
> >  .../bindings/cache/sifive,ccache0.yaml        |  44 ++-
> >  .../sifive,plic-1.0.0.yaml                    |   1 +
> >  .../devicetree/bindings/riscv/cpus.yaml       |   1 +
> >  .../devicetree/bindings/riscv/eswin.yaml      |  29 ++
> >  .../bindings/timer/sifive,clint.yaml          |   1 +
> >  .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
> >  MAINTAINERS                                   |   9 +
> >  arch/riscv/Kconfig.socs                       |   6 +
> >  arch/riscv/boot/dts/Makefile                  |   1 +
> >  arch/riscv/boot/dts/eswin/Makefile            |   2 +
> >  .../dts/eswin/eic7700-hifive-premier-p550.dts |  29 ++
> >  arch/riscv/boot/dts/eswin/eic7700.dtsi        | 345 ++++++++++++++++++
> >  drivers/cache/sifive_ccache.c                 |   2 +
> >  13 files changed, 469 insertions(+), 3 deletions(-)  create mode
> > 100644 Documentation/devicetree/bindings/riscv/eswin.yaml
> >  create mode 100644 arch/riscv/boot/dts/eswin/Makefile
> >  create mode 100644
> > arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> >  create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi
> >
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@...ts.infradead.org
> > https://nam04.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists
> > .infradead.org%2Fmailman%2Flistinfo%2Flinux-
> riscv&data=05%7C02%7Cpinke
> >
> sh.vaghela%40einfochips.com%7Caf77b3ac71d1493ae0ed08dd84d189fd%7C
> 0beb0
> >
> c359cbb4feb99e5589e415c7944%7C1%7C0%7C638812757762025060%7CUnk
> nown%7CT
> >
> WFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXa
> W4zMiI
> >
> sIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=MzOvL50ZSC
> DUcJd3Y
> > 2Cnv7L3WjqX9UxIVW7JJ%2FQ%2BWd4%3D&reserved=0