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Message-ID: <443141db-6950-4a15-83be-ad9e9c0e03a0@linaro.org>
Date: Tue, 20 May 2025 16:00:59 +0100
From: James Clark <james.clark@...aro.org>
To: Leo Yan <leo.yan@....com>
Cc: Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>,
Mark Rutland <mark.rutland@....com>, Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo <acme@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>, Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>, Jonathan Corbet <corbet@....net>,
Marc Zyngier <maz@...nel.org>, Oliver Upton <oliver.upton@...ux.dev>,
Joey Gouly <joey.gouly@....com>, Suzuki K Poulose <suzuki.poulose@....com>,
Zenghui Yu <yuzenghui@...wei.com>, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
linux-doc@...r.kernel.org, kvmarm@...ts.linux.dev
Subject: Re: [PATCH 07/10] perf: arm_spe: Add support for filtering on data
source
On 20/05/2025 2:46 pm, Leo Yan wrote:
> On Tue, May 06, 2025 at 12:41:39PM +0100, James Clark wrote:
>> SPE_FEAT_FDS adds the ability to filter on the data source of packets.
>> Like the other existing filters, enable filtering with PMSFCR_EL1.FDS
>> when any of the filter bits are set.
>>
>> Each bit maps to data sources 0-63 described by bits[0:5] in the data
>> source packet (although the full range of data source is 16 bits so
>> higher value data sources can't be filtered on). The filter is an OR of
>> all the bits, so for example setting bits 0 and 3 filters packets from
>> data sources 0 OR 3.
>
> As Arm ARM says:
>
> 0b0 : If PMSFCR_EL1.FDS is 1, do not record load operations that have
> bits [5:0] of the Data Source packet set to <m>.
> 0b1 : Load operations with Data Source <m> are unaffected by
> PMSFCR_EL1.FDS.
>
> We need extra handling for this configuration (0b0 means filtering,
> 0b1 means no affaction):
>
> - By default, the driver should set all bits in the 'data_src_filter'
> field.
>
> - The perf tool needs an extra patch in userspace to initialize all
> bits in config4 unless user specify other values.
>
> Thanks,
> Leo
>
Did you take into account PMSFCR_EL1.FDS being set automatically? I
think the wording is slightly confusing but I tested it on the model and
it works.
If PMSFCR_EL1.FDS == 0 then PMSDSFR_EL1 does nothing, and if the data
source filter isn't set by the user then FDS isn't set so there's no
need to set all the bits in the filter to 1. Once the user asks for any
filter then we set FDS, at which point it's whatever filter they asked
for. They can set all the bits if they want, or just one.
This is same way PMSFCR_EL1.FT already works. If the user asks for any
filter then it's set automatically, but we don't allow the user to ask
for "no filters" but with FT set.
So the only thing we can't do is filter out samples with _any_ data
source. Which would be PMSFCR_EL1.FDS == 1 and PMSDSFR_EL1 == 0. But I
don't think that's useful, and there are other filters to get you all or
most of the way there.
>> Signed-off-by: James Clark <james.clark@...aro.org>
>> ---
>> drivers/perf/arm_spe_pmu.c | 31 +++++++++++++++++++++++++++++++
>> 1 file changed, 31 insertions(+)
>>
>> diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
>> index 9309b846f642..d04318411f77 100644
>> --- a/drivers/perf/arm_spe_pmu.c
>> +++ b/drivers/perf/arm_spe_pmu.c
>> @@ -87,6 +87,7 @@ struct arm_spe_pmu {
>> #define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6)
>> #define SPE_PMU_FEAT_DISCARD (1UL << 7)
>> #define SPE_PMU_FEAT_EFT (1UL << 8)
>> +#define SPE_PMU_FEAT_FDS (1UL << 9)
>> #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63)
>> u64 features;
>>
>> @@ -232,6 +233,10 @@ static const struct attribute_group arm_spe_pmu_cap_group = {
>> #define ATTR_CFG_FLD_inv_event_filter_LO 0
>> #define ATTR_CFG_FLD_inv_event_filter_HI 63
>>
>> +#define ATTR_CFG_FLD_data_src_filter_CFG config4 /* PMSDSFR_EL1 */
>> +#define ATTR_CFG_FLD_data_src_filter_LO 0
>> +#define ATTR_CFG_FLD_data_src_filter_HI 63
>> +
>> GEN_PMU_FORMAT_ATTR(ts_enable);
>> GEN_PMU_FORMAT_ATTR(pa_enable);
>> GEN_PMU_FORMAT_ATTR(pct_enable);
>> @@ -248,6 +253,7 @@ GEN_PMU_FORMAT_ATTR(float_filter);
>> GEN_PMU_FORMAT_ATTR(float_filter_mask);
>> GEN_PMU_FORMAT_ATTR(event_filter);
>> GEN_PMU_FORMAT_ATTR(inv_event_filter);
>> +GEN_PMU_FORMAT_ATTR(data_src_filter);
>> GEN_PMU_FORMAT_ATTR(min_latency);
>> GEN_PMU_FORMAT_ATTR(discard);
>>
>> @@ -268,6 +274,7 @@ static struct attribute *arm_spe_pmu_formats_attr[] = {
>> &format_attr_float_filter_mask.attr,
>> &format_attr_event_filter.attr,
>> &format_attr_inv_event_filter.attr,
>> + &format_attr_data_src_filter.attr,
>> &format_attr_min_latency.attr,
>> &format_attr_discard.attr,
>> NULL,
>> @@ -286,6 +293,9 @@ static umode_t arm_spe_pmu_format_attr_is_visible(struct kobject *kobj,
>> if (attr == &format_attr_inv_event_filter.attr && !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT))
>> return 0;
>>
>> + if (attr == &format_attr_data_src_filter.attr && !(spe_pmu->features & SPE_PMU_FEAT_FDS))
>> + return 0;
>> +
>> if ((attr == &format_attr_branch_filter_mask.attr ||
>> attr == &format_attr_load_filter_mask.attr ||
>> attr == &format_attr_store_filter_mask.attr ||
>> @@ -406,6 +416,9 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *event)
>> if (ATTR_CFG_GET_FLD(attr, inv_event_filter))
>> reg |= PMSFCR_EL1_FnE;
>>
>> + if (ATTR_CFG_GET_FLD(attr, data_src_filter))
>> + reg |= PMSFCR_EL1_FDS;
>> +
>> if (ATTR_CFG_GET_FLD(attr, min_latency))
>> reg |= PMSFCR_EL1_FL;
>>
>> @@ -430,6 +443,12 @@ static u64 arm_spe_event_to_pmslatfr(struct perf_event *event)
>> return FIELD_PREP(PMSLATFR_EL1_MINLAT, ATTR_CFG_GET_FLD(attr, min_latency));
>> }
>>
>> +static u64 arm_spe_event_to_pmsdsfr(struct perf_event *event)
>> +{
>> + struct perf_event_attr *attr = &event->attr;
>> + return ATTR_CFG_GET_FLD(attr, data_src_filter);
>> +}
>> +
>> static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len)
>> {
>> struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
>> @@ -788,6 +807,10 @@ static int arm_spe_pmu_event_init(struct perf_event *event)
>> if (arm_spe_event_to_pmsnevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver))
>> return -EOPNOTSUPP;
>>
>> + if (arm_spe_event_to_pmsdsfr(event) &&
>> + !(spe_pmu->features & SPE_PMU_FEAT_FDS))
>> + return -EOPNOTSUPP;
>> +
>> if (attr->exclude_idle)
>> return -EOPNOTSUPP;
>>
>> @@ -857,6 +880,11 @@ static void arm_spe_pmu_start(struct perf_event *event, int flags)
>> write_sysreg_s(reg, SYS_PMSNEVFR_EL1);
>> }
>>
>> + if (spe_pmu->features & SPE_PMU_FEAT_FDS) {
>> + reg = arm_spe_event_to_pmsdsfr(event);
>> + write_sysreg_s(reg, SYS_PMSDSFR_EL1);
>> + }
>> +
>> reg = arm_spe_event_to_pmslatfr(event);
>> write_sysreg_s(reg, SYS_PMSLATFR_EL1);
>>
>> @@ -1116,6 +1144,9 @@ static void __arm_spe_pmu_dev_probe(void *info)
>> if (FIELD_GET(PMSIDR_EL1_EFT, reg))
>> spe_pmu->features |= SPE_PMU_FEAT_EFT;
>>
>> + if (FIELD_GET(PMSIDR_EL1_FDS, reg))
>> + spe_pmu->features |= SPE_PMU_FEAT_FDS;
>> +
>> /* This field has a spaced out encoding, so just use a look-up */
>> fld = FIELD_GET(PMSIDR_EL1_INTERVAL, reg);
>> switch (fld) {
>>
>> --
>> 2.34.1
>>
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