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Message-Id: <20250520171510.3524216-3-hugo@hugovil.com>
Date: Tue, 20 May 2025 13:15:10 -0400
From: Hugo Villeneuve <hugo@...ovil.com>
To: biju.das.jz@...renesas.com,
maarten.lankhorst@...ux.intel.com,
mripard@...nel.org,
tzimmermann@...e.de,
airlied@...il.com,
simona@...ll.ch
Cc: dri-devel@...ts.freedesktop.org,
linux-renesas-soc@...r.kernel.org,
linux-kernel@...r.kernel.org,
hugo@...ovil.com,
Hugo Villeneuve <hvilleneuve@...onoff.com>,
Chris Brandt <chris.brandt@...esas.com>
Subject: [PATCH 2/2] drm: rcar-du: rzg2l_mipi_dsi: Set DCS maximum return packet size
From: Hugo Villeneuve <hvilleneuve@...onoff.com>
The default value of 1 will result in long read commands payload not being
saved to memory.
Fix by setting this value to the DMA buffer size.
Cc: Biju Das <biju.das.jz@...renesas.com>
Cc: Chris Brandt <chris.brandt@...esas.com>
Signed-off-by: Hugo Villeneuve <hvilleneuve@...onoff.com>
---
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 10 ++++++++++
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 4 ++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
index 77d3a31ff8e35..bfff17e55d126 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
@@ -547,6 +547,7 @@ static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
const struct drm_display_mode *mode;
struct drm_connector *connector;
struct drm_crtc *crtc;
+ u32 value;
int ret;
connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
@@ -559,6 +560,15 @@ static void rzg2l_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
rzg2l_mipi_dsi_set_display_timing(dsi, mode);
+ /*
+ * The default value of 1 will result in long read commands payload
+ * not being saved to memory. Set to the DMA buffer size.
+ */
+ value = rzg2l_mipi_dsi_link_read(dsi, DSISETR);
+ value &= ~DSISETR_MRPSZ;
+ value |= FIELD_PREP(DSISETR_MRPSZ, RZG2L_DCS_BUF_SIZE);
+ rzg2l_mipi_dsi_link_write(dsi, DSISETR, value);
+
ret = rzg2l_mipi_dsi_start_hs_clock(dsi);
if (ret < 0)
goto err_stop;
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
index 33cd669bc74b1..0a783d1ea8fe1 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
@@ -81,6 +81,10 @@
#define RSTSR_SWRSTLP (1 << 1)
#define RSTSR_SWRSTHS (1 << 0)
+/* DSI Set Register */
+#define DSISETR 0x120
+#define DSISETR_MRPSZ GENMASK(15, 0)
+
/* Rx Result Save Slot 0 Register */
#define RXRSS0R 0x240
#define RXRSS0R_RXPKTDFAIL BIT(28)
--
2.39.5
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