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Message-ID: <CAHk-=whdFESwxUMvyMGuXzpCA6cm0d5kAc57fGWkWs0DLEi9qw@mail.gmail.com>
Date: Tue, 20 May 2025 11:28:28 -0700
From: Linus Torvalds <torvalds@...ux-foundation.org>
To: Borislav Petkov <bp@...en8.de>
Cc: Ard Biesheuvel <ardb@...nel.org>, "Kirill A. Shutemov" <kirill@...temov.name>, 
	Ard Biesheuvel <ardb+git@...gle.com>, linux-kernel@...r.kernel.org, x86@...nel.org, 
	Ingo Molnar <mingo@...nel.org>, Brian Gerst <brgerst@...il.com>
Subject: Re: [PATCH v5 2/7] x86/mm: Use a single cache hot per-CPU variable to
 record pgdir_shift

On Tue, 20 May 2025 at 11:01, Borislav Petkov <bp@...en8.de> wrote:
>
> OMG. :-)
>
> # 32 "./arch/x86/include/asm/pgtable_64_types.h" 1
>         movb %gs:__pgdir_shift(%rip), %al       #, pfo_val__
> # 0 "" 2
> # ./arch/x86/include/asm/pgtable.h:1178:        if (!pgtable_l5_enabled())
> #NO_APP
>         testb   $1, %al #, pfo_val__

That's garbage.

Gcc should be able to turn it into just a

        testb $1,%gs:__pgdir_shift(%rip)

What happens if pgtable_l5_enabled() is made to use  __raw_cpu_read()?
With a compiler that is new enough to support USE_X86_SEG_SUPPORT?

Oh, and it looks like we messed up __raw_cpu_read_stable(), because
that *always* uses the inline asm, so it doesn't allow the compiler to
just DTRT and do things like the above.

                Linus

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