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Message-ID: <78563998-8257-4f7a-8fe1-cf9372c348d5@linaro.org>
Date: Tue, 20 May 2025 10:03:59 +0200
From: neil.armstrong@...aro.org
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
Rob Clark <robdclark@...il.com>, Abhinav Kumar <quic_abhinavk@...cinc.com>,
Sean Paul <sean@...rly.run>, Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Vinod Koul <vkoul@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Subject: Re: [PATCH v4 23/30] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >= 7 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8 ++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 ++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 6 ++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 ++----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
> 12 files changed, 21 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index 9a8f6043370997cb12414c4132eb68cc73f7030a..013314b2e716a6d939393b77b0edc87170dba27b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -286,32 +286,30 @@ static const struct dpu_dsc_cfg sm8650_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_2_0", .id = DSC_4,
> .base = 0x82000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_2_1", .id = DSC_5,
> .base = 0x82000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index e81a2a02e0a6379382058fd89500cf2064a2193f..b4d41e2644349bdbdbdacbe1e9b3748f90df4f3b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -263,22 +263,20 @@ static const struct dpu_dsc_cfg sm8350_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index b0e94ccf7f83e9c3c41f1df363cb6a8c24f1503d..5d88f0261d8320a78f8d64c9bb68b938f83160a0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 2cf30234e45da8a7776d61c49c26abd75d070941..303d33dc7783ac91a496fa0a19860564ad0b6d5d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -262,32 +262,28 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_2_0", .id = DSC_4,
> .base = 0x82000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_2_1", .id = DSC_5,
> .base = 0x82000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index dcef56683224b5715c2608b5472d2d5a0da62010..3c0728a4b37ea6af25ab64315cfe63ba6f8d2774 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -276,22 +276,20 @@ static const struct dpu_dsc_cfg sm8450_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> index 5f5987d5fc602df29c5eb289823de5dd359df014..b8a1646395916fde04b9750cf548edca5729d9c2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> @@ -275,32 +275,28 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_2_0", .id = DSC_4,
> .base = 0x82000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_2_1", .id = DSC_5,
> .base = 0x82000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 6f310216fbccb985308f617db20c1878e622340a..ef22a9adf43ddc9d15be5f1359ea5f6690e9f27c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index ba8a2c5dc5e2b3474b295c86afbbbe8f8d416ccd..2e7d4403835353927bc85a5acd3e6c5967cac455 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg sar2130p_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index 77986a7bd62c1b6323482426e596e5974ba40865..ac95d46b3ecf2d95ec0d516a79567fe9c204b5f6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index cc17b20a7d4c15b0cd9c5dc8b9a4b78d4cb78315..01430ff90ab0988bdaa91b85458dd649aab543b3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -176,13 +176,11 @@ enum {
> * DSC sub-blocks/features
> * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets
> * the pixel output from this DSC.
> - * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2
> * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding
> * @DPU_DSC_MAX
> */
> enum {
> DPU_DSC_OUTPUT_CTRL = 0x1,
> - DPU_DSC_HW_REV_1_2,
> DPU_DSC_NATIVE_42x_EN,
> DPU_DSC_MAX
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 80ffd46cbfe69fc90afcdc1a144fc5de7bb6af42..d478a7bce7568ab000d73467bcad91e29f049abc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1043,7 +1043,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
> msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base,
> "%s", cat->dsc[i].name);
>
> - if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) {
> + if (cat->mdss_ver->core_major_ver >= 7) {
> struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc;
> struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl;
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 7bcb1e057b143a5512aafbd640199c8f3b436527..c2a659512cb747e1dd5ed9e28534286ff8d67f4f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -168,7 +168,7 @@ int dpu_rm_init(struct drm_device *dev,
> struct dpu_hw_dsc *hw;
> const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
>
> - if (test_bit(DPU_DSC_HW_REV_1_2, &dsc->features))
> + if (cat->mdss_ver->core_major_ver >= 7)
> hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);
> else
> hw = dpu_hw_dsc_init(dev, dsc, mmio);
>
Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>
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