linux-kernel - Re: [PATCH 1/2] dt-bindings: stm32: add STM32MP21 clocks and reset bindings

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Message-ID: <8fc2a770-4940-4275-8080-27ef53ec3d2d@foss.st.com>
Date: Tue, 20 May 2025 15:53:43 +0200
From: Gabriel FERNANDEZ <gabriel.fernandez@...s.st.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Michael Turquette
	<mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring
	<robh+dt@...nel.org>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue
	<alexandre.torgue@...s.st.com>,
        Philipp Zabel <p.zabel@...gutronix.de>
CC: <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
        Nicolas Le Bayon <nicolas.le.bayon@...com>
Subject: Re: [PATCH 1/2] dt-bindings: stm32: add STM32MP21 clocks and reset
 bindings


On 5/19/25 16:38, Krzysztof Kozlowski wrote:
> On 19/05/2025 16:20, gabriel.fernandez@...s.st.com wrote:
>> From: Gabriel Fernandez <gabriel.fernandez@...s.st.com>
>>
>> Adds clock and reset binding entries for STM32MP21 SoC family.
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@...s.st.com>
>> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@...com>
>
> I am pretty sure I gave to ST this feedback already:
>
> You CC-ed an address, which suggests you do not work on mainline kernel
> or you do not use get_maintainers.pl/b4/patman. Please rebase and always
> work on mainline or start using mentioned tools, so correct addresses
> will be used.

Hi Krzysztof, many thanks for your review

Sorry for this bad manipulation, i will use b4 tools.


>> ---
>>   .../bindings/clock/st,stm32mp21-rcc.yaml      | 200 ++++++++
>>   include/dt-bindings/clock/st,stm32mp21-rcc.h  | 428 ++++++++++++++++++
>>   include/dt-bindings/reset/st,stm32mp21-rcc.h  | 140 ++++++
>>   3 files changed, 768 insertions(+)
> ...
>
>> +
>> +  access-controllers:
>> +    minItems: 1
>> +    maxItems: 2
> List the items.
ok
>
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - '#clock-cells'
>> +  - '#reset-cells'
>> +  - clocks
>
> ...
>
>> +#define CK_KER_FMC		263
>> +#define CK_KER_SDMMC1		264
>> +#define CK_KER_SDMMC2		265
>> +#define CK_KER_SDMMC3		266
>> +#define CK_KER_ETH1		267
>> +#define CK_KER_ETH2		268
>> +#define CK_KER_ETH1PTP		269
>> +#define CK_KER_ETH2PTP		270
>> +#define CK_KER_USB2PHY1		271
>> +#define CK_KER_USB2PHY2		272
>> +#define CK_MCO1			273
>> +#define CK_MCO2			274
>> +#define CK_KER_DTS		275
>> +#define CK_ETH1_RX		276
>> +#define CK_ETH1_TX		277
>> +#define CK_ETH1_MAC		278
>> +#define CK_ETH2_RX		279
>> +#define CK_ETH2_TX		280
>> +#define CK_ETH2_MAC		281
>> +#define CK_ETH1_STP		282
>> +#define CK_ETH2_STP		283
>> +#define CK_KER_LTDC		284
>> +#define HSE_DIV2_CK		285
>> +#define CK_DBGMCU		286
>> +#define CK_DAP			287
>> +#define CK_KER_ETR		288
>> +#define CK_KER_STM		289
>> +
>> +#define STM32MP21_LAST_CLK	290
> Drop

ok


>> +
>
> ...
>
>> +#define DDR_R		113
>> +#define DDRPERFM_R	114
>> +#define IWDG1_SYS_R	116
>> +#define IWDG2_SYS_R	117
>> +#define IWDG3_SYS_R	118
>> +#define IWDG4_SYS_R	119
>> +
>> +#define STM32MP21_LAST_RESET	120
> Drop

ok

Best regards,

Gabriel

>
>> +
>> +#define RST_SCMI_C1_R		0
>> +#define RST_SCMI_C2_R		1
>> +#define RST_SCMI_C1_HOLDBOOT_R	2
>> +#define RST_SCMI_C2_HOLDBOOT_R	3
>> +#define RST_SCMI_FMC		4
>> +#define RST_SCMI_OSPI1		5
>> +#define RST_SCMI_OSPI1DLL	6
>> +
>> +#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */
>
> Best regards,
> Krzysztof