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Message-ID: <79e7ad17-4496-47fe-aec6-d64dcee7dc43@foss.st.com>
Date: Tue, 20 May 2025 15:56:29 +0200
From: Gabriel FERNANDEZ <gabriel.fernandez@...s.st.com>
To: ALOK TIWARI <alok.a.tiwari@...cle.com>,
Michael Turquette
<mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring
<robh+dt@...nel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue
<alexandre.torgue@...s.st.com>,
Philipp Zabel <p.zabel@...gutronix.de>
CC: <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
Nicolas Le Bayon <nicolas.le.bayon@...com>
Subject: Re: [PATCH 2/2] clk: stm32: introduce clocks for STM32MP21 platform
On 5/19/25 17:36, ALOK TIWARI wrote:
>
>
> On 19-05-2025 19:50, gabriel.fernandez@...s.st.com wrote:
>> From: Gabriel Fernandez <gabriel.fernandez@...s.st.com>
>>
>> This driver is intended for the STM32MP21 clock family.
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@...s.st.com>
>> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@...com>
>> ---
>> drivers/clk/stm32/Kconfig | 7 +
>> drivers/clk/stm32/Makefile | 1 +
>> drivers/clk/stm32/clk-stm32mp21.c | 1583 +++++++++++++++++++++++++++++
>> drivers/clk/stm32/stm32mp21_rcc.h | 651 ++++++++++++
>> 4 files changed, 2242 insertions(+)
>> create mode 100644 drivers/clk/stm32/clk-stm32mp21.c
>> create mode 100644 drivers/clk/stm32/stm32mp21_rcc.h
>>
>> diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig
>> index dca409d52652..12396f1c5cec 100644
>> --- a/drivers/clk/stm32/Kconfig
>> +++ b/drivers/clk/stm32/Kconfig
>> @@ -25,6 +25,13 @@ config COMMON_CLK_STM32MP157
>> help
>> Support for stm32mp15x SoC family clocks.
>> +config COMMON_CLK_STM32MP215
>> + bool "Clock driver for stm32m21x clocks"
>
> should not be stm32mp21x?
yes
>
>> + depends on ARM || ARM64 || COMPILE_TEST
>> + default y
>> + help
>> + Support for stm32mp21x SoC family clocks
>> +
>> config COMMON_CLK_STM32MP257
>> bool "Clock driver for stm32mp25x clocks"
>> depends on ARM64 || COMPILE_TEST
>> diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile
>> index 0a627164fcce..e04727b59449 100644
>> --- a/drivers/clk/stm32/Makefile
>> +++ b/drivers/clk/stm32/Makefile
>> @@ -1,3 +1,4 @@
>> obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o
>> clk-stm32-core.o reset-stm32.o
>> obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o reset-stm32.o
>> +obj-$(CONFIG_COMMON_CLK_STM32MP215) += clk-stm32mp21.o
>> clk-stm32-core.o reset-stm32.o
>> obj-$(CONFIG_COMMON_CLK_STM32MP257) += clk-stm32mp25.o
>> clk-stm32-core.o reset-stm32.o
>> diff --git a/drivers/clk/stm32/clk-stm32mp21.c
>> b/drivers/clk/stm32/clk-stm32mp21.c
>> new file mode 100644
> [clip]
>> +#define RCC_R30SEMCR 0x124
>> +#define RCC_R31CIDCFGR 0x128
>> +#define RCC_R31SEMCR 0x12C
>> +#define RCC_R32CIDCFGR 0x130
>> +#define RCC_R32SEMCR 0x134
>> +#define RCC_R33CIDCFGR 0x138
>> +#define RCC_R33SEMCR 0x13C
>> +#define RCC_R34CIDCFGR 0x140
>> +#define RCC_R34SEMCR 0x144
>> +#define RCC_R35CIDCFGR 0x148
>> +#define RCC_R35SEMCR 0x14C
>> +#define RCC_R36CIDCFGR 0x150
>> +#define RCC_R36SEMCR 0x154
>> +#define RCC_R37CIDCFGR 0x158
>> +#define RCC_R37SEMCR 0x15C
>> +#define RCC_R38CIDCFGR 0x160
>> +#define RCC_R38SEMCR 0x164
>> +#define RCC_R39CIDCFGR 0x168
>> +#define RCC_R39SEMCR 0x16C
>> +#define RCC_R40CIDCFGR 0x170
>> +#define RCC_R40SEMCR 0x174
>> +#define RCC_R41CIDCFGR 0x178
>> +#define RCC_R41SEMCR 0x17C
>> +#define RCC_R42CIDCFGR 0x180
>> +#define RCC_R42SEMCR 0x184
>> +#define RCC_R43CIDCFGR 0x188
>> +#define RCC_R43SEMCR 0x18C
>> +#define RCC_R44CIDCFGR 0x190
>> +#define RCC_R44SEMCR 0x194
>> +#define RCC_R45CIDCFGR 0x198
>> +#define RCC_R45SEMCR 0x19C
>> +#define RCC_R46CIDCFGR 0x1A0
>> +#define RCC_R46SEMCR 0x1A4
>> +#define RCC_R47CIDCFGR 0x1A8
>> +#define RCC_R47SEMCR 0x1AC
>> +#define RCC_R48CIDCFGR 0x1B0
>> +#define RCC_R48SEMCR 0x1B4
>> +#define RCC_R49CIDCFGR 0x1B8
>> +#define RCC_R49SEMCR 0x1BC
>> +#define RCC_R50CIDCFGR 0x1C0
>> +#define RCC_R50SEMCR 0x1C4
>> +#define RCC_R51CIDCFGR 0x1C8
>> +#define RCC_R51SEMCR 0x1CC
>> +#define RCC_R52CIDCFGR 0x1D0
>> +#define RCC_R52SEMCR 0x1D4
>> +#define RCC_R53CIDCFGR 0x1D8
>> +#define RCC_R53SEMCR 0x1DC
>> +#define RCC_R54CIDCFGR 0x1E0
>> +#define RCC_R54SEMCR 0x1E4
>> +#define RCC_R55CIDCFGR 0x1E8
>> +#define RCC_R55SEMCR 0x1EC
>> +#define RCC_R56CIDCFGR 0x1F0
>> +#define RCC_R56SEMCR 0x1F4
>> +#define RCC_R57CIDCFGR 0x1F8
>> +#define RCC_R57SEMCR 0x1FC
>> +#define RCC_R58CIDCFGR 0x200
>> +#define RCC_R58SEMCR 0x204
>> +#define RCC_R59CIDCFGR 0x208
>> +#define RCC_R59SEMCR 0x20C
>> +#define RCC_R60CIDCFGR 0x210
>> +#define RCC_R60SEMCR 0x214
>> +#define RCC_R61CIDCFGR 0x218
>> +#define RCC_R61SEMCR 0x21C
>> +#define RCC_R62CIDCFGR 0x220
>> +#define RCC_R62SEMCR 0x224
>> +#define RCC_R63CIDCFGR 0x228
>> +#define RCC_R63SEMCR 0x22C
>> +#define RCC_R64CIDCFGR 0x230
>> +#define RCC_R64SEMCR 0x234
>> +#define RCC_R65CIDCFGR 0x238
>> +#define RCC_R65SEMCR 0x23C
>> +#define RCC_R66CIDCFGR 0x240
>> +#define RCC_R66SEMCR 0x244
>> +#define RCC_R67CIDCFGR 0x248
>> +#define RCC_R67SEMCR 0x24C
>> +#define RCC_R68CIDCFGR 0x250
>> +#define RCC_R68SEMCR 0x254
>> +#define RCC_R69CIDCFGR 0x258
>> +#define RCC_R69SEMCR 0x25C
>> +#define RCC_R70CIDCFGR 0x260
>> +#define RCC_R70SEMCR 0x264
>> +#define RCC_R71CIDCFGR 0x268
>> +#define RCC_R71SEMCR 0x26C
>
> 0x270 and 0x274 , not here
> is this typo or intentional ?
>
These registers are reserved.
Thanks for review
Gabriel
>> +#define RCC_R73CIDCFGR 0x278
>> +#define RCC_R73SEMCR 0x27C
>> +#define RCC_R74CIDCFGR 0x280
>> +#define RCC_R74SEMCR 0x284
>> +#define RCC_R75CIDCFGR 0x288
>> +#define RCC_R75SEMCR 0x28C
>> +#define RCC_R76CIDCFGR 0x290
>> +#define RCC_R76SEMCR 0x294
>> +#define RCC_R77CIDCFGR 0x298
>> +#define RCC_R77SEMCR 0x29C
>> +#define RCC_R78CIDCFGR 0x2A0
>> +#define RCC_R78SEMCR 0x2A4
>> +#define RCC_R79CIDCFGR 0x2A8
>> +#define RCC_R79SEMCR 0x2AC
>> +#define RCC_R83CIDCFGR 0x2C8
>
> Thanks,
> Alok
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