linux-kernel - Re: [PATCH v3 5/5] arm64: dts: rockchip: Add naneng-combphy for RK3528

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Message-ID: <aC059MLlfeUT2a18@pie>
Date: Wed, 21 May 2025 02:27:00 +0000
From: Yao Zi <ziyao@...root.org>
To: Jonas Karlman <jonas@...boo.se>
Cc: Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Heiko Stuebner <heiko@...ech.de>,
	Frank Wang <frank.wang@...k-chips.com>,
	Andy Yan <andy.yan@...k-chips.com>,
	Cristian Ciocaltea <cristian.ciocaltea@...labora.com>,
	Detlev Casanova <detlev.casanova@...labora.com>,
	Shresth Prasad <shresthprasad7@...il.com>,
	Chukun Pan <amadeus@....edu.cn>, linux-phy@...ts.infradead.org,
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 5/5] arm64: dts: rockchip: Add naneng-combphy for
 RK3528

On Tue, May 20, 2025 at 07:51:57PM +0200, Jonas Karlman wrote:
> On 2025-05-19 18:16, Yao Zi wrote:
> > Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB
> > 3.0 controllers. Describe it and the pipe-phy grf which it depends on.
> > 
> > Signed-off-by: Yao Zi <ziyao@...root.org>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3528.dtsi | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > index b2724c969a76..314afb94e19b 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > @@ -318,6 +318,11 @@ vpu_grf: syscon@...40000 {
> >  			reg = <0x0 0xff340000 0x0 0x8000>;
> >  		};
> >  
> > +		pipe_phy_grf: syscon@...48000 {
> > +			compatible = "rockchip,rk3528-pipe-phy-grf", "syscon";
> > +			reg = <0x0 0xff348000 0x0 0x8000>;
> > +		};
> > +
> >  		vo_grf: syscon@...60000 {
> >  			compatible = "rockchip,rk3528-vo-grf", "syscon";
> >  			reg = <0x0 0xff360000 0x0 0x10000>;
> > @@ -867,6 +872,23 @@ dmac: dma-controller@...60000 {
> >  			arm,pl330-periph-burst;
> >  		};
> >  
> > +		combphy: phy@...c0000 {
> > +			compatible = "rockchip,rk3528-naneng-combphy";
> > +			reg = <0x0 0xffdc0000 0x0 0x10000>;
> > +			#phy-cells = <1>;
> 
> Should probably be sorted at end or before resets prop.

Will sort the properties.

> 
> > +			clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>,
> This break the ~80 line length limit mostly kept in this file.

Oops, I didn't notice it. Will split them into lines.

> > +				 <&cru PCLK_PIPE_GRF>;
> > +			clock-names = "ref", "apb",
> > +				      "pipe";
> 
> Could be kept on a single line.
> 
> > +			assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
> > +			assigned-clock-rates = <100000000>;
> 
> Other assigned-clock props are sorted before clocks props in this file.
> 
> This is also missing power-domains information (also missing from
> dt-bindings patch):
> 
> 	power-domains = <&power RK3528_PD_VPU>;

I didn't expect your power-domain series when writing v1, thanks for the
reminder.

As the power-domain series just came out, I'd like to wait until it
merges and then work further on RK3528 support for naneng-combphy.

I'm not sure whether it's possible to get the combphy cleanup patch (3th
in this series) merged first. It should be ready for merging and I think
this may avoid possible conflicts in the future, Any suggestions will be
appreciated.

> > +			resets = <&cru SRST_PCIE_PIPE_PHY>, <&cru SRST_P_PCIE_PHY>;
> 
> This also break the ~80 line length limit mostly kept in this file.

I'm willing to keep the ~80 limit and will split the line.

> Regards,
> Jonas
> 
> > +			reset-names = "phy", "apb";
> > +			rockchip,pipe-grf = <&vpu_grf>;
> > +			rockchip,pipe-phy-grf = <&pipe_phy_grf>;
> > +			status = "disabled";
> > +		};
> > +
> >  		pinctrl: pinctrl {
> >  			compatible = "rockchip,rk3528-pinctrl";
> >  			rockchip,grf = <&ioc_grf>;
> 

Best regards,
Yao Zi