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Message-ID: <174784256989.406.9397007136555067613.tip-bot2@tip-bot2>
Date: Wed, 21 May 2025 15:49:29 -0000
From: "tip-bot2 for Rob Herring (Arm)" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: "Rob Herring (Arm)" <robh@...nel.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>, x86@...nel.org,
linux-kernel@...r.kernel.org
Subject:
[tip: timers/clocksource] dt-bindings: timer: Convert jcore,pit to DT schema
The following commit has been merged into the timers/clocksource branch of tip:
Commit-ID: f8470be859a8660c1993fa44053c473c82eb454b
Gitweb: https://git.kernel.org/tip/f8470be859a8660c1993fa44053c473c82eb454b
Author: Rob Herring (Arm) <robh@...nel.org>
AuthorDate: Mon, 05 May 2025 21:22:52 -05:00
Committer: Daniel Lezcano <daniel.lezcano@...aro.org>
CommitterDate: Fri, 16 May 2025 11:10:33 +02:00
dt-bindings: timer: Convert jcore,pit to DT schema
Convert the J-Core PIT Timer binding to DT schema format. It's a
straight-forward conversion.
Since the 'reg' entries are based on number of cores, we can't put
constraints on it.
Signed-off-by: Rob Herring (Arm) <robh@...nel.org>
Link: https://lore.kernel.org/r/20250506022253.2587999-1-robh@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
---
Documentation/devicetree/bindings/timer/jcore,pit.txt | 24 +-----
Documentation/devicetree/bindings/timer/jcore,pit.yaml | 43 +++++++++-
2 files changed, 43 insertions(+), 24 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.yaml
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
deleted file mode 100644
index af5dd35..0000000
--- a/Documentation/devicetree/bindings/timer/jcore,pit.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-J-Core Programmable Interval Timer and Clocksource
-
-Required properties:
-
-- compatible: Must be "jcore,pit".
-
-- reg: Memory region(s) for timer/clocksource registers. For SMP,
- there should be one region per cpu, indexed by the sequential,
- zero-based hardware cpu number.
-
-- interrupts: An interrupt to assign for the timer. The actual pit
- core is integrated with the aic and allows the timer interrupt
- assignment to be programmed by software, but this property is
- required in order to reserve an interrupt number that doesn't
- conflict with other devices.
-
-
-Example:
-
-timer@200 {
- compatible = "jcore,pit";
- reg = < 0x200 0x30 0x500 0x30 >;
- interrupts = < 0x48 >;
-};
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.yaml b/Documentation/devicetree/bindings/timer/jcore,pit.yaml
new file mode 100644
index 0000000..9e6e25b
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/jcore,pit.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/jcore,pit.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: J-Core Programmable Interval Timer and Clocksource
+
+maintainers:
+ - Rich Felker <dalias@...c.org>
+
+properties:
+ compatible:
+ const: jcore,pit
+
+ reg:
+ description:
+ Memory region(s) for timer/clocksource registers. For SMP, there should be
+ one region per cpu, indexed by the sequential, zero-based hardware cpu
+ number.
+
+ interrupts:
+ description:
+ An interrupt to assign for the timer. The actual pit core is integrated
+ with the aic and allows the timer interrupt assignment to be programmed by
+ software, but this property is required in order to reserve an interrupt
+ number that doesn't conflict with other devices.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@200 {
+ compatible = "jcore,pit";
+ reg = <0x200 0x30 0x500 0x30>;
+ interrupts = <0x48>;
+ };
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