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Message-ID: <aC4w4WmPywIEsMwk@google.com>
Date: Wed, 21 May 2025 13:00:33 -0700
From: Namhyung Kim <namhyung@...nel.org>
To: Mingwei Zhang <mizhang@...gle.com>
Cc: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	Sean Christopherson <seanjc@...gle.com>,
	Paolo Bonzini <pbonzini@...hat.com>,
	Mark Rutland <mark.rutland@....com>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Jiri Olsa <jolsa@...nel.org>, Ian Rogers <irogers@...gle.com>,
	Adrian Hunter <adrian.hunter@...el.com>, Liang@...gle.com,
	Kan <kan.liang@...ux.intel.com>, "H. Peter Anvin" <hpa@...or.com>,
	linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
	kvm@...r.kernel.org, linux-kselftest@...r.kernel.org,
	Yongwei Ma <yongwei.ma@...el.com>,
	Xiong Zhang <xiong.y.zhang@...ux.intel.com>,
	Dapeng Mi <dapeng1.mi@...ux.intel.com>,
	Jim Mattson <jmattson@...gle.com>,
	Sandipan Das <sandipan.das@....com>,
	Zide Chen <zide.chen@...el.com>,
	Eranian Stephane <eranian@...gle.com>,
	Shukla Manali <Manali.Shukla@....com>,
	Nikunj Dadhania <nikunj.dadhania@....com>
Subject: Re: [PATCH v4 34/38] perf/x86/amd: Support
 PERF_PMU_CAP_MEDIATED_VPMU for AMD host

On Mon, Mar 24, 2025 at 05:31:14PM +0000, Mingwei Zhang wrote:
> From: Sandipan Das <sandipan.das@....com>
> 
> Apply the PERF_PMU_CAP_MEDIATED_VPMU flag for version 2 and later
> implementations of the core PMU. Aside from having Global Control and
> Status registers, virtualizing the PMU using the passthrough model
> requires an interface to set or clear the overflow bits in the Global
> Status MSRs while restoring or saving the PMU context of a vCPU.
> 
> PerfMonV2-capable hardware has additional MSRs for this purpose namely,
> PerfCntrGlobalStatusSet and PerfCntrGlobalStatusClr, thereby making it
> suitable for use with mediated vPMU.

So IBS cannot be used in the guest (with MEDIATED_VPMU) and host can
profile guests with it, right?

Thanks,
Namhyung

> 
> Signed-off-by: Sandipan Das <sandipan.das@....com>
> Signed-off-by: Mingwei Zhang <mizhang@...gle.com>
> ---
>  arch/x86/events/amd/core.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index 30d6ceb4c8ad..a8b537dd2ddb 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -1433,6 +1433,8 @@ static int __init amd_core_pmu_init(void)
>  
>  		amd_pmu_global_cntr_mask = x86_pmu.cntr_mask64;
>  
> +		x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU;
> +
>  		/* Update PMC handling functions */
>  		x86_pmu.enable_all = amd_pmu_v2_enable_all;
>  		x86_pmu.disable_all = amd_pmu_v2_disable_all;
> -- 
> 2.49.0.395.g12beb8f557-goog
> 

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