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Message-ID: <20250521-quixotic-jackdaw-of-certainty-ac02dd@kuoka>
Date: Wed, 21 May 2025 11:09:44 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Shubhi Garg <shgarg@...dia.com>
Cc: jonathanh@...dia.com, lee@...nel.org, robh@...nel.org,
alexandre.belloni@...tlin.com, thierry.reding@...il.com, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 1/6] dt-bindings: mfd: add bindings for NVIDIA VRS PSEQ
On Tue, May 20, 2025 at 09:08:27AM GMT, Shubhi Garg wrote:
> Add bindings for NVIDIA VRS (Voltage Regulator Specification) power
> sequencer device. NVIDIA VRS PSEQ controls ON/OFF and suspend/resume
> power sequencing of system power rails on Tegra234 SoC. This device
> also provides 32kHz RTC support with backup battery for system timing.
>
A nit, subject: drop second/last, redundant "bindings for". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
> Signed-off-by: Shubhi Garg <shgarg@...dia.com>
> ---
>
> v2:
> - fixed copyrights
> - updated description with RTC information
> - added status node in dtb node example
>
> .../bindings/mfd/nvidia,vrs-pseq.yaml | 60 +++++++++++++++++++
> 1 file changed, 60 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml b/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml
> new file mode 100644
> index 000000000000..676a29d4e1fa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/nvidia,vrs-pseq.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Voltage Regulator Specification Power Sequencer
> +
> +maintainers:
> + - Shubhi Garg <shgarg@...dia.com>
> +
> +description:
> + NVIDIA Voltage Regulator Specification Power Sequencer device controls
> + ON/OFF and suspend/resume power sequencing of system power rails for NVIDIA
> + SoCs. It provides 32kHz RTC clock support with backup battery for system
> + timing. The device also acts as an interrupt controller for managing
> + interrupts from the VRS power sequencer.
> +
> +properties:
> + compatible:
> + const: nvidia,vrs-pseq
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
Use consistent quotes, either ' or "
> + const: 2
> + description:
> + The first cell is the IRQ number, the second cell is the trigger type.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-controller
> + - "#interrupt-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vrs@3c {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
e.g. pmic@ or something appropriate.
> + compatible = "nvidia,vrs-pseq";
> + reg = <0x3c>;
> + interrupt-parent = <&pmc>;
> + interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
Mixed up indentation.
Best regards,
Krzysztof
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