linux-kernel - Re: [net PATCH 1/2] octeontx2-af: Set LMT

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Message-ID:
 <CH0PR18MB4339446EDBF8869C2740AEC0CD9EA@CH0PR18MB4339.namprd18.prod.outlook.com>
Date: Wed, 21 May 2025 12:00:00 +0000
From: Geethasowjanya Akula <gakula@...vell.com>
To: Michal Swiatkowski <michal.swiatkowski@...ux.intel.com>
CC: "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "davem@...emloft.net"
	<davem@...emloft.net>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        "edumazet@...gle.com" <edumazet@...gle.com>,
        "andrew+netdev@...n.ch"
	<andrew+netdev@...n.ch>,
        Sunil Kovvuri Goutham <sgoutham@...vell.com>,
        Subbaraya Sundeep Bhatta <sbhatta@...vell.com>,
        Hariprasad Kelam
	<hkelam@...vell.com>
Subject: Re: [net PATCH 1/2] octeontx2-af: Set LMT_ENA bit for APR table
 entries



>-----Original Message-----
>From: Michal Swiatkowski <michal.swiatkowski@...ux.intel.com>
>Sent: Wednesday, May 21, 2025 2:10 PM
>To: Geethasowjanya Akula <gakula@...vell.com>
>Cc: netdev@...r.kernel.org; linux-kernel@...r.kernel.org; kuba@...nel.org;
>davem@...emloft.net; pabeni@...hat.com; edumazet@...gle.com;
>andrew+netdev@...n.ch; Sunil Kovvuri Goutham <sgoutham@...vell.com>;
>Subbaraya Sundeep Bhatta <sbhatta@...vell.com>; Hariprasad Kelam
><hkelam@...vell.com>
>Subject: [EXTERNAL] Re: [net PATCH 1/2] octeontx2-af: Set LMT_ENA bit for APR
>table entries
>
>On Wed, May 21, 2025 at 11:38:33AM +0530, Geetha sowjanya wrote:
>> From: Subbaraya Sundeep <sbhatta@...vell.com>
>>
>> This patch enables the LMT line for a PF/VF by setting the LMT_ENA bit
>> in the APR_LMT_MAP_ENTRY_S structure.
>>
>> Additionally, it simplifies the logic for calculating the LMTST table
>> index by consistently using the maximum number of hw supported VFs
>> (i.e., 256).
>>
>> Fixes: 873a1e3d207a ("octeontx2-af: cn10k: Setting up lmtst map table").
>> Signed-off-by: Subbaraya Sundeep <sbhatta@...vell.com>
>> Signed-off-by: Geetha sowjanya <gakula@...vell.com>
>> ---
>>  .../net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 15
>> +++++++++++++--
>>  1 file changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> index 7fa98aeb3663..3838c04b78c2 100644
>> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
>> @@ -15,13 +15,17 @@
>>  #define LMT_TBL_OP_WRITE	1
>>  #define LMT_MAP_TABLE_SIZE	(128 * 1024)
>>  #define LMT_MAPTBL_ENTRY_SIZE	16
>> +#define LMT_MAX_VFS		256
>> +
>> +#define LMT_MAP_ENTRY_ENA      BIT_ULL(20)
>> +#define LMT_MAP_ENTRY_LINES    GENMASK_ULL(18, 16)
>>
>>  /* Function to perform operations (read/write) on lmtst map table */
>> static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
>>  			       int lmt_tbl_op)
>>  {
>>  	void __iomem *lmt_map_base;
>> -	u64 tbl_base;
>> +	u64 tbl_base, cfg;
>>
>>  	tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
>>
>> @@ -35,6 +39,13 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32
>index, u64 *val,
>>  		*val = readq(lmt_map_base + index);
>>  	} else {
>>  		writeq((*val), (lmt_map_base + index));
>> +
>> +		cfg = FIELD_PREP(LMT_MAP_ENTRY_ENA, 0x1);
>> +		/* 2048 LMTLINES */
>> +		cfg |= FIELD_PREP(LMT_MAP_ENTRY_LINES, 0x6);
>> +
>> +		writeq(cfg, (lmt_map_base + (index + 8)));
>Is this 8 LMT_MAP_TBL_W1_OFF? It isn't obvious for me why +8, but I don't
>know the driver, so maybe it should.
The APR table entry is 16B wide. The  ENTRY_ENA and ENTRY_LINES fields falls in upper 8B.
Hence doing +8.

Thanks,
Geetha.
>
>> +
>>  		/* Flushing the AP interceptor cache to make
>APR_LMT_MAP_ENTRY_S
>>  		 * changes effective. Write 1 for flush and read is being used as
>a
>>  		 * barrier and sets up a data dependency. Write to 0 after a
>write
>> @@ -52,7 +63,7 @@ static int lmtst_map_table_ops(struct rvu *rvu, u32
>> index, u64 *val,  #define LMT_MAP_TBL_W1_OFF  8  static u32
>> rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc)  {
>> -	return ((rvu_get_pf(pcifunc) * rvu->hw->total_vfs) +
>> +	return ((rvu_get_pf(pcifunc) * LMT_MAX_VFS) +
>>  		(pcifunc & RVU_PFVF_FUNC_MASK)) *
>LMT_MAPTBL_ENTRY_SIZE;
>
>Just nit/question, patch looks fine
>Reviewed-by: Michal Swiatkowski <michal.swiatkowski@...ux.intel.com>
>
>>  }
>>
>> --
>> 2.25.1