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Message-ID: <20250521-upstream_rcc_mp21-v3-3-cac9d8f63d20@foss.st.com>
Date: Wed, 21 May 2025 14:38:51 +0200
From: Gabriel Fernandez <gabriel.fernandez@...s.st.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski
<krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Maxime Coquelin
<mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Philipp Zabel <p.zabel@...gutronix.de>
CC: <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
Gabriel Fernandez <gabriel.fernandez@...s.st.com>
Subject: [PATCH v3 3/3] dt-bindings: stm32: cosmetic fixes for STM32MP25
clock and reset bindings
- drop minItems from access-controllers
- remove rcc label from example
- fixes typos
- remove double '::' from 'See also::'
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@...s.st.com>
---
.../devicetree/bindings/clock/st,stm32mp25-rcc.yaml | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml
index 88e52f10d1ecc68e818cd7d8cb1ca39dceb7a494..1e3b5d218bb01acb247d27bc6902be821cabd98c 100644
--- a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml
+++ b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml
@@ -11,9 +11,9 @@ maintainers:
description: |
The RCC hardware block is both a reset and a clock controller.
- RCC makes also power management (resume/supend).
+ RCC makes also power management (resume/suspend).
- See also::
+ See also:
include/dt-bindings/clock/st,stm32mp25-rcc.h
include/dt-bindings/reset/st,stm32mp25-rcc.h
@@ -38,7 +38,7 @@ properties:
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
- - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)
+ - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
@@ -108,15 +108,14 @@ properties:
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
- - description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub
+ - description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
- description: CK_SCMI_PLL3 PLL3 clock
- description: clk_dsi_txbyte DSI byte clock
access-controllers:
- minItems: 1
- maxItems: 2
+ maxItems: 1
required:
- compatible
@@ -131,7 +130,7 @@ examples:
- |
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
- rcc: clock-controller@...00000 {
+ clock-controller@...00000 {
compatible = "st,stm32mp25-rcc";
reg = <0x44200000 0x10000>;
#clock-cells = <1>;
--
2.25.1
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