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Message-ID: <77278a5d-e606-4a6b-b88d-d17968d7ab31@altera.com>
Date: Thu, 22 May 2025 14:38:45 -0700
From: Matthew Gerlach <matthew.gerlach@...era.com>
To: Rob Herring <robh@...nel.org>
Cc: andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com,
kuba@...nel.org, pabeni@...hat.com, krzk+dt@...nel.org, conor+dt@...nel.org,
mturquette@...libre.com, richardcochran@...il.com, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Mun Yew Tham <mun.yew.tham@...era.com>
Subject: Re: [PATCH] dt-bindings: net: Convert socfpga-dwmac bindings to yaml
On 5/20/25 12:52 PM, Rob Herring wrote:
> On Tue, May 13, 2025 at 08:22:37AM -0700, Matthew Gerlach wrote:
> > From: Mun Yew Tham <mun.yew.tham@...era.com>
> >
> > Convert the bindings for socfpga-dwmac to yaml.
> >
> > Signed-off-by: Mun Yew Tham <mun.yew.tham@...era.com>
> > Signed-off-by: Matthew Gerlach <matthew.gerlach@...era.com>
> > ---
> > .../bindings/net/socfpga,dwmac.yaml | 109 ++++++++++++++++++
> > .../devicetree/bindings/net/socfpga-dwmac.txt | 57 ---------
> > 2 files changed, 109 insertions(+), 57 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/net/socfpga,dwmac.yaml
> > delete mode 100644 Documentation/devicetree/bindings/net/socfpga-dwmac.txt
> >
> > diff --git a/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml b/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml
> > new file mode 100644
> > index 000000000000..68ad580dc2da
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/socfpga,dwmac.yaml
> > @@ -0,0 +1,109 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/socfpga,dwmac.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Altera SOCFPGA SoC DWMAC controller
> > +
> > +maintainers:
> > + - Matthew Gerlach <matthew.gerlach@...era.com>
> > +
> > +select:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - altr,socfpga-stmmac
> > + - altr,socfpga-stmmac-a10-s10
> > + required:
> > + - altr,sysmgr-syscon
>
> Should be 'compatible' here.
Yes, compatible should be here.
>
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: altr,socfpga-stmmac
> > + - const: snps,dwmac-3.70a
> > + - const: snps,dwmac
> > + - items:
> > + - const: altr,socfpga-stmmac-a10-s10
> > + - const: snps,dwmac-3.74a
> > + - const: snps,dwmac
> > + - items:
> > + - const: altr,socfpga-stmmac-a10-s10
> > + - const: snps,dwmac-3.72a
> > + - const: snps,dwmac
>
> The last 2 lists can be combined.
Yes, the last 2 lists can be combined, but I'm also thinking of dropping
the last list, for now. The last list represents the Arria10 with the
following relevant dtsi:
arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
The problem with the Arria10 is the 'reset-names = "stmmaceth",
"stmmaceth-ocp";' property fails the oneOf: check for reset-names in
snps,dwmac.yaml. I don't really want to change the old dtsi, and I don't
think changing snps,dwmac.yaml is correct either. So I might leave out
Arria10 support in this submission. Any suggestions would be appreciated.
>
> > +
> > + clocks:
> > + minItems: 1
> > + maxItems: 4
>
> You need to define what each entry is.
I will add descriptions for the entries.
>
> > +
> > + clock-names:
> > + minItems: 1
> > + maxItems: 4
>
> And the name for each entry.
I will list the names too.
>
> > +
> > + phy-mode:
> > + enum:
> > + - rgmii
> > + - sgmii
> > + - gmii
> > +
> > + altr,emac-splitter:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + Should be the phandle to the emac splitter soft IP node if DWMAC
> > + controller is connected an emac splitter.
> > +
> > + altr,f2h_ptp_ref_clk:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + Phandle to Precision Time Protocol reference clock. This clock is
> > + common to gmac instances and defaults to osc1.
> > +
> > + altr,gmii-to-sgmii-converter:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + Should be the phandle to the gmii to sgmii converter soft IP.
> > +
> > + altr,sysmgr-syscon:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description:
> > + Should be the phandle to the system manager node that encompass
> > + the glue register, the register offset, and the register shift.
> > + On Cyclone5/Arria5, the register shift represents the PHY mode
> > + bits, while on the Arria10/Stratix10/Agilex platforms, the
> > + register shift represents bit for each emac to enable/disable
> > + signals from the FPGA fabric to the EMAC modules.
> > + minItems: 1
> > + items:
> > + - description: phandle to the system manager node
> > + - description: offset of the control register
> > + - description: shift within the control register
>
> items:
> - items:
> - description: phandle to the system manager node
> - ...
> - ...
>
> And drop minItems.
I will update these too.
>
> > +
> > +allOf:
> > + - $ref: snps,dwmac.yaml#
> > +
> > +additionalProperties: true
>
> unevaluatedProperties: false
>
> > +
> > +examples:
> > +
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + soc {
> > + #address-cells = <1>;
>
> Use 4 space indent.
>
> > + #size-cells = <1>;
> > + gmac0: ethernet@...00000 {
>
> Drop the label.
I will fix the indent and drop the label.
Thanks for the review,
Matthew Gerlach
>
> > + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
> > + "snps,dwmac";
> > + altr,sysmgr-syscon = <&sysmgr 0x60 0>;
> > + reg = <0xff700000 0x2000>;
> > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq";
> > + mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
> > + clocks = <&emac_0_clk>;
> > + clock-names = "stmmaceth";
> > + phy-mode = "sgmii";
> > + };
> > + };
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