linux-kernel - [PATCH v8 19/20] PCI/AER: Add ratelimits to PCI AER Documentation

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Message-ID: <20250522232339.1525671-20-helgaas@kernel.org>
Date: Thu, 22 May 2025 18:21:25 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: linux-pci@...r.kernel.org
Cc: Jon Pan-Doh <pandoh@...gle.com>,
	Karolina Stolarek <karolina.stolarek@...cle.com>,
	Weinan Liu <wnliu@...gle.com>,
	Martin Petersen <martin.petersen@...cle.com>,
	Ben Fuller <ben.fuller@...cle.com>,
	Drew Walton <drewwalton@...rosoft.com>,
	Anil Agrawal <anilagrawal@...a.com>,
	Tony Luck <tony.luck@...el.com>,
	Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
	Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@...ux.intel.com>,
	Lukas Wunner <lukas@...ner.de>,
	Jonathan Cameron <Jonathan.Cameron@...wei.com>,
	Sargun Dhillon <sargun@...a.com>,
	"Paul E . McKenney" <paulmck@...nel.org>,
	Mahesh J Salgaonkar <mahesh@...ux.ibm.com>,
	Oliver O'Halloran <oohall@...il.com>,
	Kai-Heng Feng <kaihengf@...dia.com>,
	Keith Busch <kbusch@...nel.org>,
	Robert Richter <rrichter@....com>,
	Terry Bowman <terry.bowman@....com>,
	Shiju Jose <shiju.jose@...wei.com>,
	Dave Jiang <dave.jiang@...el.com>,
	linux-kernel@...r.kernel.org,
	linuxppc-dev@...ts.ozlabs.org,
	Krzysztof Wilczyński <kwilczynski@...nel.org>,
	Bjorn Helgaas <bhelgaas@...gle.com>
Subject: [PATCH v8 19/20] PCI/AER: Add ratelimits to PCI AER Documentation

From: Jon Pan-Doh <pandoh@...gle.com>

Add ratelimits section for rationale and defaults.

[bhelgaas: note fatal errors are not ratelimited]

Signed-off-by: Karolina Stolarek <karolina.stolarek@...cle.com>
Signed-off-by: Jon Pan-Doh <pandoh@...gle.com>
Tested-by: Krzysztof Wilczyński <kwilczynski@...nel.org>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@...ux.intel.com>
Acked-by: Paul E. McKenney <paulmck@...nel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@...gle.com>
Link: https://patch.msgid.link/20250520215047.1350603-17-helgaas@kernel.org
---
 Documentation/PCI/pcieaer-howto.rst | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/PCI/pcieaer-howto.rst b/Documentation/PCI/pcieaer-howto.rst
index f013f3b27c82..6fb31516fff1 100644
--- a/Documentation/PCI/pcieaer-howto.rst
+++ b/Documentation/PCI/pcieaer-howto.rst
@@ -85,6 +85,18 @@ In the example, 'Requester ID' means the ID of the device that sent
 the error message to the Root Port. Please refer to PCIe specs for other
 fields.
 
+AER Ratelimits
+--------------
+
+Since error messages can be generated for each transaction, we may see
+large volumes of errors reported. To prevent spammy devices from flooding
+the console/stalling execution, messages are throttled by device and error
+type (correctable vs. non-fatal uncorrectable).  Fatal errors, including
+DPC errors, are not ratelimited.
+
+AER uses the default ratelimit of DEFAULT_RATELIMIT_BURST (10 events) over
+DEFAULT_RATELIMIT_INTERVAL (5 seconds).
+
 AER Statistics / Counters
 -------------------------
 
-- 
2.43.0