[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20250523-b4-ctr_upstream_v3-v3-7-ad355304ba1c@rivosinc.com>
Date: Fri, 23 May 2025 00:25:13 +0100
From: Rajnesh Kanwal <rkanwal@...osinc.com>
To: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Namhyung Kim <namhyung@...nel.org>, Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>, Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>, Atish Kumar Patra <atishp@...osinc.com>,
Anup Patel <anup@...infault.org>, Will Deacon <will@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Beeman Strong <beeman@...osinc.com>
Cc: linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org,
Palmer Dabbelt <palmer@...ive.com>, Conor Dooley <conor@...nel.org>,
devicetree@...r.kernel.org, Rajnesh Kanwal <rkanwal@...osinc.com>
Subject: [PATCH v3 7/7] dt-bindings: riscv: add Sxctr ISA extension
description
Add the S[m|s]ctr ISA extension description.
Signed-off-by: Rajnesh Kanwal <rkanwal@...osinc.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index f34bc66940c06bf9b3c18fcd7cce7bfd0593cd28..193751400933ca3fe69e0b2bc03e9c635e2db244 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -149,6 +149,13 @@ properties:
to enable privilege mode filtering for cycle and instret counters as
ratified in the 20240326 version of the privileged ISA specification.
+ - const: smctr
+ description: |
+ The standard Smctr supervisor-level extension for the machine mode
+ to enable recording limited branch history in a register-accessible
+ internal core storage as ratified at commit 9c87013 ("Merge pull
+ request #44 from riscv/issue-42-fix") of riscv-control-transfer-records.
+
- const: smmpm
description: |
The standard Smmpm extension for M-mode pointer masking as
@@ -196,6 +203,13 @@ properties:
and mode-based filtering as ratified at commit 01d1df0 ("Add ability
to manually trigger workflow. (#2)") of riscv-count-overflow.
+ - const: ssctr
+ description: |
+ The standard Ssctr supervisor-level extension for recording limited
+ branch history in a register-accessible internal core storage as
+ ratified at commit 9c87013 ("Merge pull request #44 from
+ riscv/issue-42-fix") of riscv-control-transfer-records.
+
- const: ssnpm
description: |
The standard Ssnpm extension for next-mode pointer masking as
@@ -740,6 +754,20 @@ properties:
const: zihpm
- contains:
const: zicntr
+ # Smctr depends on Sscsrind
+ - if:
+ contains:
+ const: smctr
+ then:
+ contains:
+ const: sscsrind
+ # Ssctr depends on Sscsrind
+ - if:
+ contains:
+ const: ssctr
+ then:
+ contains:
+ const: sscsrind
allOf:
# Zcf extension does not exist on rv64
--
2.43.0
Powered by blists - more mailing lists