linux-kernel - Re: [PATCH v9 02/10] dt-bindings: clock: Add cpg for the Renesas RZ/T2H SoC

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Message-ID: <CAMuHMdXv_1nXmRkTfB9i95wjSXaN2XjQG2f55ZNV6axeNUmpzg@mail.gmail.com>
Date: Fri, 23 May 2025 12:00:37 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Thierry Bultel <thierry.bultel.yh@...renesas.com>
Cc: thierry.bultel@...atsea.fr, linux-renesas-soc@...r.kernel.org, 
	paul.barker.ct@...renesas.com, Rob Herring <robh@...nel.org>, linux-clk@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v9 02/10] dt-bindings: clock: Add cpg for the Renesas
 RZ/T2H SoC

On Thu, 15 May 2025 at 16:18, Thierry Bultel
<thierry.bultel.yh@...renesas.com> wrote:
> Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.
>
> Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
> ---
> Changes v8->v9:
>   - keep clock names in generic section because T2H is a subset
>   - removed R9A09G077_CLK_BSC, to only keep R9A09G077_CLK_CKIO
>   - removed R9A09G077_MSTP* macros and module clocks definitions

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in a branch shared by renesas-clk for v6.17 and
renesas-devel for v6.17.


> Changes v7->v8:
>   - extra parenthesis
>   - added loco
>   - renesas-cpg-mssr.h: removed unused clocks, added a macro for mstp
> Changes v6->v7:
>   - Add description for reg property
> Changes v5->v6:
>   - Set clock minItem constraint
>   - Moved additionalProperties after 'allOf' section
> Changes v4->v5:
>   - Set reg minItems and maxItems defaults at top level
> Changes v3->v4:
>   - Handle maxItems and clocks names properly in schema.
> ---
>  .../bindings/clock/renesas,cpg-mssr.yaml      | 46 ++++++++++++++-----
>  .../clock/renesas,r9a09g077-cpg-mssr.h        | 28 +++++++++++
>  2 files changed, 63 insertions(+), 11 deletions(-)
>  create mode 100644 include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> index 77ce3615c65a..708ab6bd7d44 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> @@ -52,9 +52,15 @@ properties:
>        - renesas,r8a779f0-cpg-mssr # R-Car S4-8
>        - renesas,r8a779g0-cpg-mssr # R-Car V4H
>        - renesas,r8a779h0-cpg-mssr # R-Car V4M
> +      - renesas,r9a09g077-cpg-mssr # RZ/T2H
>
>    reg:
> -    maxItems: 1
> +    minItems: 1
> +    items:
> +      - description: base address of register block 0
> +      - description: base address of register block 1
> +    description: base addresses of clock controller. Some controllers
> +      (like r9a09g077) use two blocks instead of a single one.
>
>    clocks:
>      minItems: 1
> @@ -92,16 +98,6 @@ properties:
>        the datasheet.
>      const: 1
>
> -if:
> -  not:
> -    properties:
> -      compatible:
> -        items:
> -          enum:
> -            - renesas,r7s9210-cpg-mssr
> -then:
> -  required:
> -    - '#reset-cells'
>
>  required:
>    - compatible
> @@ -111,6 +107,34 @@ required:
>    - '#clock-cells'
>    - '#power-domain-cells'
>
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g077-cpg-mssr
> +    then:
> +      properties:
> +        reg:
> +          minItems: 2
> +        clock-names:
> +          items:
> +            - const: extal
> +    else:
> +      properties:
> +        reg:
> +          maxItems: 1
> +  - if:
> +      not:
> +        properties:
> +          compatible:
> +            items:
> +              enum:
> +                - renesas,r7s9210-cpg-mssr
> +    then:
> +      required:
> +        - '#reset-cells'
> +
>  additionalProperties: false
>
>  examples:
> diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
> new file mode 100644
> index 000000000000..29155fb0401e
> --- /dev/null
> +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
> +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* R9A09G077 CPG Core Clocks */
> +#define R9A09G077_CLK_CA55C0           0
> +#define R9A09G077_CLK_CA55C1           1
> +#define R9A09G077_CLK_CA55C2           2
> +#define R9A09G077_CLK_CA55C3           3
> +#define R9A09G077_CLK_CA55S            4
> +#define R9A09G077_CLK_CR52_CPU0                5
> +#define R9A09G077_CLK_CR52_CPU1                6
> +#define R9A09G077_CLK_CKIO             7
> +#define R9A09G077_CLK_PCLKAH           8
> +#define R9A09G077_CLK_PCLKAM           9
> +#define R9A09G077_CLK_PCLKAL           10
> +#define R9A09G077_CLK_PCLKGPTL         11
> +#define R9A09G077_CLK_PCLKH            12
> +#define R9A09G077_CLK_PCLKM            13
> +
> +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
> --
> 2.43.0
>


--
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds