linux-kernel - Re: [PATCH v2] riscv: vector: Fix context save/restore with xtheadvector

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Message-ID: <CAFTtA3MaXonbwnVpCPiOZKem86pkxdPcdxjdQqC5Ywrd8RMHSQ@mail.gmail.com>
Date: Sat, 24 May 2025 17:58:50 +0800
From: Andy Chiu <andybnac@...il.com>
To: Han Gao <rabenda.cn@...il.com>
Cc: linux-riscv@...ts.infradead.org, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Alexandre Ghiti <alex@...ti.fr>, Charlie Jenkins <charlie@...osinc.com>, Jesse Taube <jesse@...osinc.com>, 
	Conor Dooley <conor.dooley@...rochip.com>, 
	Xiongchuan Tan <tanxiongchuan@...c.iscas.ac.cn>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] riscv: vector: Fix context save/restore with xtheadvector

On Fri, May 23, 2025 at 6:26 PM Han Gao <rabenda.cn@...il.com> wrote:
>
> Previously only v0-v7 were correctly saved/restored,
> and the context of v8-v31 are damanged.
> Correctly save/restore v8-v31 to avoid breaking userspace.
>
> Fixes: d863910eabaf ("riscv: vector: Support xtheadvector save/restore")
> Signed-off-by: Han Gao <rabenda.cn@...il.com>
> Tested-by: Xiongchuan Tan <tanxiongchuan@...c.iscas.ac.cn>
> Reviewed-by: Charlie Jenkins <charlie@...osinc.com>

Reviewed-by: Andy Chiu <andybnac@...il.com>

> ---
>
> Changes in v2:
>   Add fix tag
>   Improve commit mesage
>
> v1: https://lore.kernel.org/linux-riscv/c221c98dc2369ea691e3eb664bf084dc909496f6.1747934680.git.rabenda.cn@gmail.com/
>
>  arch/riscv/include/asm/vector.h | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index e8a83f55be2b..7df6355023a3 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
>                         THEAD_VSETVLI_T4X0E8M8D1
>                         THEAD_VSB_V_V0T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VSB_V_V0T0
> +                       THEAD_VSB_V_V8T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VSB_V_V0T0
> +                       THEAD_VSB_V_V16T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VSB_V_V0T0
> +                       THEAD_VSB_V_V24T0
>                         : : "r" (datap) : "memory", "t0", "t4");
>         } else {
>                 asm volatile (
> @@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
>                         THEAD_VSETVLI_T4X0E8M8D1
>                         THEAD_VLB_V_V0T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VLB_V_V0T0
> +                       THEAD_VLB_V_V8T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VLB_V_V0T0
> +                       THEAD_VLB_V_V16T0
>                         "add            t0, t0, t4\n\t"
> -                       THEAD_VLB_V_V0T0
> +                       THEAD_VLB_V_V24T0
>                         : : "r" (datap) : "memory", "t0", "t4");
>         } else {
>                 asm volatile (
> --
> 2.47.2
>