linux-kernel - [PATCH 2/2] arm64: dts: renesas: r8a779g3: Describe split PCIe clock on V4H Sparrow Hawk

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Message-ID: <20250525160513.83029-2-marek.vasut+renesas@mailbox.org>
Date: Sun, 25 May 2025 18:04:04 +0200
From: Marek Vasut <marek.vasut+renesas@...lbox.org>
To: linux-arm-kernel@...ts.infradead.org
Cc: Marek Vasut <marek.vasut+renesas@...lbox.org>,
	Bartosz Golaszewski <brgl@...ev.pl>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Magnus Damm <magnus.damm@...il.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	Rob Herring <robh@...nel.org>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org
Subject: [PATCH 2/2] arm64: dts: renesas: r8a779g3: Describe split PCIe clock on V4H Sparrow Hawk

The V4H Sparrow Hawk board supplies PCIe controller input clock and PCIe
bus clock from separate outputs of Renesas 9FGV0441 clock generator chip.
Describe this split bus configuration in the board DT. The topology looks
as follows:

 ____________                    _____________
| R-Car PCIe |                  | PCIe device |
|            |                  |             |
|    PCIe RX<|==================|>PCIe TX     |
|    PCIe TX<|==================|>PCIe RX     |
|            |                  |             |
|   PCIe CLK<|======..  ..======|>PCIe CLK    |
'------------'      ||  ||      '-------------'
                    ||  ||
 ____________       ||  ||
|  9FGV0441  |      ||  ||
|            |      ||  ||
|   CLK DIF0<|======''  ||
|   CLK DIF1<|==========''
|   CLK DIF2<|
|   CLK DIF3<|
'------------'

Signed-off-by: Marek Vasut <marek.vasut+renesas@...lbox.org>
---
Cc: Bartosz Golaszewski <brgl@...ev.pl>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>
Cc: Conor Dooley <conor+dt@...nel.org>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>
Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>
Cc: Magnus Damm <magnus.damm@...il.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: Rob Herring <robh@...nel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>
Cc: devicetree@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: linux-pci@...r.kernel.org
Cc: linux-renesas-soc@...r.kernel.org
---
 .../dts/renesas/r8a779g3-sparrow-hawk.dts     | 45 ++++++++++++++++++-
 1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
index b8698e07add56..7c050a56290fd 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
@@ -130,6 +130,13 @@ mini_dp_con_in: endpoint {
 		};
 	};
 
+	/* Page 26 / PCIe.0/1 CLK */
+	pcie_refclk: clk-x8 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
 	reg_1p2v: regulator-1p2v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.2V";
@@ -404,6 +411,14 @@ i2c0_mux2: i2c@2 {
 			reg = <2>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+
+			/* Page 26 / PCIe.0/1 CLK */
+			pcie_clk: clk@68 {
+				compatible = "renesas,9fgv0441";
+				reg = <0x68>;
+				clocks = <&pcie_refclk>;
+				#clock-cells = <1>;
+			};
 		};
 
 		i2c0_mux3: i2c@3 {
@@ -487,24 +502,50 @@ msiof1_snd_endpoint: endpoint {
 
 /* Page 26 / 2230 Key M M.2 */
 &pcie0_clkref {
-	clock-frequency = <100000000>;
+	status = "disabled";
 };
 
 &pciec0 {
+	clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>;
 	reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 	status = "okay";
+
+	/* PCIe bridge, Root Port */
+	pci@0,0 {
+		#address-cells = <3>;
+		#size-cells = <2>;
+		reg = <0x0 0x0 0x0 0x0 0x0>;
+		compatible = "pciclass,0604";
+		device_type = "pci";
+		clocks = <&pcie_clk 1>;
+		vpcie3v3-supply = <&reg_3p3v>;
+		ranges;
+	};
 };
 
 /* Page 25 / PCIe to USB */
 &pcie1_clkref {
-	clock-frequency = <100000000>;
+	status = "disabled";
 };
 
 &pciec1 {
+	clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>;
 	/* uPD720201 is PCIe Gen2 x1 device */
 	num-lanes = <1>;
 	reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 	status = "okay";
+
+	/* PCIe bridge, Root Port */
+	pci@0,0 {
+		#address-cells = <3>;
+		#size-cells = <2>;
+		reg = <0x0 0x0 0x0 0x0 0x0>;
+		compatible = "pciclass,0604";
+		device_type = "pci";
+		clocks = <&pcie_clk 3>;
+		vpcie3v3-supply = <&reg_3p3v>;
+		ranges;
+	};
 };
 
 &pfc {
-- 
2.47.2