linux-kernel - [PATCH 1/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support

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Message-Id: <20250525-ipq5018-ge-phy-v1-1-ddab8854e253@outlook.com>
Date: Sun, 25 May 2025 21:56:04 +0400
From: George Moussalem via B4 Relay <devnull+george.moussalem.outlook.com@...nel.org>
To: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>, 
 Russell King <linux@...linux.org.uk>, 
 "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, 
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Florian Fainelli <f.fainelli@...il.com>, 
 Philipp Zabel <p.zabel@...gutronix.de>, 
 Bjorn Andersson <andersson@...nel.org>, 
 Konrad Dybcio <konradybcio@...nel.org>, 
 Michael Turquette <mturquette@...libre.com>, 
 Stephen Boyd <sboyd@...nel.org>
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org, 
 linux-clk@...r.kernel.org, George Moussalem <george.moussalem@...look.com>
Subject: [PATCH 1/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE
 PHY support

From: George Moussalem <george.moussalem@...look.com>

Document the IPQ5018 Internal Gigabit Ethernet PHY found in the IPQ5018
SoC. Its output pins provide an MDI interface to either an external
switch in a PHY to PHY link scenario or is directly attached to an RJ45
connector.

In a phy to phy architecture, DAC values need to be set to accommodate
for the short cable length. As such, add an optional property to do so.

In addition, the LDO controller found in the IPQ5018 SoC needs to be
enabled to driver low voltages to the CMN Ethernet Block (CMN BLK) which
the GE PHY depends on. The LDO must be enabled in TCSR by writing to a
specific register. So, adding a property that takes a phandle to the
TCSR node and the register offset.

Signed-off-by: George Moussalem <george.moussalem@...look.com>
---
 .../devicetree/bindings/net/qca,ar803x.yaml        | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml
index 3acd09f0da863137f8a05e435a1fd28a536c2acd..a9e94666ff0af107db4f358b144bf8644c6597e8 100644
--- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml
+++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml
@@ -60,6 +60,29 @@ properties:
     minimum: 1
     maximum: 255

+  qca,dac:
+    description:
+      Values for MDAC and EDAC to adjust amplitude, bias current settings,
+      and error detection and correction algorithm. Only set in a PHY to PHY
+      link architecture to accommodate for short cable length.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    items:
+      - items:
+          - description: value for MDAC. Expected 0x10, if set
+          - description: value for EDAC. Expected 0x10, if set
+      - maxItems: 1
+
+  qca,eth-ldo-enable:
+    description:
+      Register in TCSR to enable the LDO controller to supply
+      low voltages to the common ethernet block (CMN BLK).
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle of TCSR syscon
+          - description: offset of TCSR register to enable the LDO controller
+      - maxItems: 1
+
   vddio-supply:
     description: |
       RGMII I/O voltage regulator (see regulator/regulator.yaml).

-- 
2.49.0