lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [day] [month] [year] [list]
Message-ID: <20250526134149.3239623-1-markus.stockhausen@gmx.de>
Date: Mon, 26 May 2025 09:41:49 -0400
From: Markus Stockhausen <markus.stockhausen@....de>
To: tsbogend@...ha.franken.de,
	tglx@...utronix.de,
	linux-mips@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	s.gottschall@...wrt.com
Cc: Markus Stockhausen <markus.stockhausen@....de>
Subject: [PATCH v2] irqchip/mips-gic: allow forced affinity

Devices of the Realtek MIPS Otto platform use the official rtl-otto-timer
as clock event generator and cpu clocksource. It is registered for cpu
startup via cpuhp_setup_state() and forces the affinity of the clockevent
interrupts to the appropriate cpu via irq_force_affinity().

On the "smaller" devices with a vendor specific interrupt controller
(supported by irq-realtek-rtl) the registration works fine. The "larger"
RTL931x series is based on a MIPS interAptiv dual core with a MIPS GIC
controller. Interrupt routing setup is cancelled because gic_set_affinity()
does not accept the current (not yet online) cpu as a target.

Relax the checks by evaluating the force parameter that is provided for
exactly this purpose like in other drivers. With this patch affinity can
be set as follows:

- force = false: allow to set affinity to any online cpu
- force = true: allow to set affinity to any cpu

Signed-off-by: Markus Stockhausen <markus.stockhausen@....de>
Signed-off-by: Sebastian Gottschall <s.gottschall@...wrt.com>
---
 drivers/irqchip/irq-mips-gic.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index bca8053864b2..1c2284297354 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -375,9 +375,13 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 	/*
 	 * The GIC specifies that we can only route an interrupt to one VP(E),
 	 * ie. CPU in Linux parlance, at a time. Therefore we always route to
-	 * the first online CPU in the mask.
+	 * the first forced or online CPU in the mask.
 	 */
-	cpu = cpumask_first_and(cpumask, cpu_online_mask);
+	if (force)
+		cpu = cpumask_first(cpumask);
+	else
+		cpu = cpumask_first_and(cpumask, cpu_online_mask);
+
 	if (cpu >= NR_CPUS)
 		return -EINVAL;
 
-- 
2.47.0


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ